Chung Woo Kim

Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.

The Effects of ONO thickness on Memory Characteristics in Nano-scale Charge Trapping Devices

In the use of single/few electrons in distributed storage for nonvolatile, low power and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has a radicn dependence and we are working with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and evaluate the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of low doped drain (LDD) process is investigated to draw these conclusions.

Ultrashort SONOS memories

We report the operational characteristics of ultrashort SONOS memories down to /spl sim/30-nm effective gate length. Good sub-threshold swing, good drain-induced barrier lowering (/spl sim/120 mV/decade), and /spl sim/2.4 V of memory window down to the smallest dimensions demonstrate the improvements that result from a thin tunneling oxide and a large trapping center density. The use of distributed defects and thin tunneling oxide is reflected in a memory window that is stable up to at least 10/sup 5/ cycles for the smallest devices. The smallest structures tested employ /spl sim/75 electrons for memory storage, which allows for device to device reproducibility. The capture and emission processes asymmetries point to the differences in the energy parameters of the two processes. The smallest structures, however, do show loss of retention time compared to the larger structures, for the same oxide-nitride-oxide stack thickness, and this is believed to arise from higher leakage due to higher defects distribution in the gate insulators from process-induced damage. All tested devices, down to /spl sim/30-nm effective gate length, show very good endurance characteristics.

Triple high /spl kappa/ stacks (Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/) with high pressure (10 atm) H/sub 2/ and D/sub 2/ annealing for SONOS type flash memory device applications

In this article, we report on electrical and memory properties of triple high-/spl kappa/ stacks (Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/) with high pressure (10 atm) H/sub 2/ and D/sub 2/ annealing for SONOS type flash memory device applications. For 3 nm-thick Al/sub 2/O/sub 3//10 nm-thick HfO/sub 2//10 nm-thick Al/sub 2/O/sub 3/ (AHA) stack, memory window (M.W.) of 1.4 V at programming/erasing (P/E) condition of /spl plusmn/6 V/1-2 msec was obtained. In addition, high pressure D/sub 2/ annealed sample shows improved retention characteristics such as large memory window, and low slope per decade with retention time.

Multi-bit functional NOR type SONOS memories

We show that nearly 90 electrons can be stored at 30 nm dimensions of memory nodes, sufficient for reproducibility with having multi-bit memory windows, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. This work has achieved ultra-low number of electron storage while achieving high threshold shifts and demonstrates predictability through self-consistent modeling of programming and erasure characteristics.

A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatile Memories

Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) [1] and nano-crystal memory [2] have been considered as a replacement floating gate memory due to simple process, low voltage operation and high speed. In the SONOS memory, an ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention. This may allow longer retention with thinner tunneling dielectrics, leading to lower operating voltages. However for the high speed performance, SONOS needs improvement in erase time the discharging process of electrons from the traps. Thus we have speculated on the effect of electric fields in the trapping-control gate region, and characterized the effects of doping on poly-silicon gate in SONOS memory device. Our experiments compare the characteristics of SONOS memories between n+ type and p+ type polysilicon gate. Figure 1 shows the schematics of these structures. SONOS memory devices have been fabricated with 0.5 um n+ type gate or p+ type gate on SOI substrates using the conventional CMOS processing technology. The tunneling oxide of 3 nm thickness was grown at 900 C and then a Si3N4 film of 5.5 nm and the blocking oxide layer of 7 nm were deposited by low pressure chemical vapor deposition (LPCVD). Figure 2 shows a transmission-electron micrograph of the cross-section of this grown and deposited memory stack with the dark region as the silicon nitride. After these gate stacks process, n+ type or p+ type poly-silicon is deposited. Using the program/erase threshold voltage window as 4 V in p+ type poly-silicon gate memory, the program time is approximately 20 us at 16 V program voltage and the erase time is about 1 ms at a –16 V erase voltage using FN tunneling method. The capture and erase characteristics also show asymmetries in the capture and erase processes due to the physical differences in the processes themselves. The capture process is based on Fowler-Nordheim injection where the relevant capture cross-section is related to the extent of the potential perturbation of the defect. This capture crosssection is one to two orders of magnitude smaller than that of silicon nanocrystals. The erasure process is presumably a Poole-Frenkel mechanism, or other similar de-trapping process with strong localization and field-dependence. The erase time of SONOS memory device is somewhat slow, and it is due to the injection of electrons through top oxide from the gate and heavy mass of holes. To solve this problem, several methods have been introduced recently. Using a high k material instead of SiO2 thin film is useful for decreasing the transmission of electrons in the top oxide due to the capacitive coupling [3]. However, this may not be suitable technologically in a CMOS process. We expect that the higher work-function of p-type gate to improve erase speed. Figure 4 shows that the erase speed of p+ gate is much faster than that of n+ gate. The work will describe detailed experimental measurements in support of this conclusion.

The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices

In the use of single/few electrons in distributed storage for non-volatile, low power, and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has dependence and the devices operate with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of LDD process are investigated to draw these conclusions.