Chunqi Shi

A single-chip CMOS UHF RFID reader transceiver

UHF RFID reader transceiver for Chinese local standard (840-845 MHz and 920-925 MHz), in concord with the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C, is presented. A highly linear RF front-end with low flicker noise, an on-chip self-jammer cancellation (SC) circuit with fast time-varying cut-off frequency and a DC-offset cancellation (DCOC) circuit are proposed to deal with the large self-jammer in the receiver. In the presence of 22 dBm PA output power, the receiver achieves a sensitivity of -79 dBm including the 15 dB loss of the directional coupler. A CMOS class-AB PA is integrated in the transmitter, with 22 dBm output power and 35% PAE. The spectrum mask achieves ACPR1 of -45 dBc and ACPR2 of -60 dBc . A sigma-delta fractional-N PLL with a single LC VCO is also implemented for good phase noise (-126 dBc/Hz @ 1 MHz offset) and high frequency resolution within 1 kHz. This single-chip is fabricated in a 0.18 standard CMOS process. It occupies a silicon area of 13.5 mm2 and dissipates 203 mW from a 1.8 V supply voltage when transmitting 7.5 dBm output power.

A 0.8–2.5GHz wideband SiGe BiCMOS low noise amplifier with noise fiugre of 1.98–3.3dB

This paper presents an optimized 0.8–2.5GHz low noise amplifier for wideband applications. Based on cascade structure, a shunt resistive feedback with an emitter degeneration inductor is used. Both low noise figure and high gain are achieved simultaneously. Measured results show that the proposed LNA has a maximum gain of 19.6dB at 0.8GHz and a minimum gain of 14.3dB at 2.5GHz. The noise figure varies from 1.98 to 3.3dB among the whole band. The overall power supply is 24mw at 3V supply and the occupied die area is only 0.4mm2.

A low-phase-noise frequency synthesizer for single chip CMOS UHF RFID reader

A novel fractional-N frequency synthesizer which is based on delta sigma modulator (DSM) and specialized for single-chip ultra-high frequency radio-frequency identification (UHF RFID) reader is proposed in this paper. The fractional-N synthesizer is implemented in 0.18 mum CMOS process. The phase noise of the fractional-N synthesizer is approximately -109 dBc/Hz and -129 dBc/Hz at 200 kHz and 1 MHz offset from 900 MHz operating frequency while drawing 9.6 mA from 1.8 V power supply. The synthesizer is evaluated by implementing it in a direct conversion RF front-end. The front-end features a noise figure of 3.5 dB and an input-referred third-order intercept point of 5 dBm.

A single-chip UHF RFID reader transceiver for mobile applications

A single-chip UHF RFID reader transceiver for mobile applications has been fabricated in 0.18μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2C with fully-compliant China 800/900MHz RFID draft, ISO/IEC 18000-6C protocol and ETSI 302 208-1 local regulation. The receiver in the presence of -3dBm self-jammer achieves -75dBm 1% PER sensitivity. The linear class-A PA integrated in transmitter has 25dBm OP1dB output power for CW. The fully-integrated fractional-N frequency synthesizer is designed based on MASH 1-1-1 sigma-delta modulator and 1.8GHz fundamental frequency LC-VCO for lower in-band and out-of-band phase noise. The measured phase noise is up to -106.2dBc/Hz at 200kHz offset and -130.2dBc/Hz at 1MHz offset from center frequency and the integrated RMS jitter from 10kHz to 10MHz is less than 1.6pS. The whole chip dissipates 330mA from 3.3V power supply when transmitting 22.4dBm CW signal and the PAE of linear PA is up to 26%. The chip area is 16.8mm2.

Several key issues in single-chip UHF RFID reader design

Several key issues including system noise figure, input linearity, LO phase noise performance and transceiver setting-up time are recapitulated in this paper for the design of singlechip UHF RFID reader. The reader Rx noise figure is different between LBT and normal mode. The input linearity is decided by the maximum interferer due to Tx-to-Rx leakage. Phase noise requirements are to meet with Tx transmission spectrum mask, and withhold adjacent interferer and in-band self-jammer. The transceiver setting-up time is determined by the larger value between frequency synthesizer switching time and DC-offset removal time. A low-power low-cost single-chip 0.18μm CMOS UHF RFID reader transceiver is verified based on the foregoing analyses.

Design of a wideband and low phase noise LC VCO

In this paper, a 3.18∼4.258GHz wideband and low phase noise LC VCO is proposed. Three binary-weighted switching capacitors are exploited to expand the bandwidth; On-chip LDO is utilized to suppress noise from power supply. Symmetrical noise filtering technique is used to suppress thermal noise from tail current and parasitic resistors of bonding wires. The circuit is implemented with 0.13µm RF CMOS process. The frequency tuning range is from 3.18GHz to 4.258GHz and phase noise is −120dBc/Hz at IMHz offset from 4.258GHz carrier. The Figure of Merit (FOM) is −181dB/Hz and maximum power consumption is 12.5mW.

A Low Noise VCO with Quadrature Prescaler for UHF RFID Reader

A low phase noise CMOS LC VCO working at 1.8GHz with quadrature prescaler for single-chip UHF 860-960MHz RFID Reader is proposed in this paper. The symmetrical filtration technology is adopted to suppress noise for complementary cross coupled LC VCO. FOM method is applied in low-noise VCO design. Injection locked prescaler with ring oscillator core can provide wide locking range. The proposed LC VCO and prescaler are implemented in IBM 0.18μm RF CMOS technology. The measurement results show that the VCO achieves a phase noise of -132dBc/Hz at 1MHz offset from 1.8GHz while drawing 10.5mA from a 3.3V power supply. The tuning range of the proposed LC VCO covers from 1.71GHz to 2.19GHz. The locking range of the proposed prescaler is 66.35% with in-phase and quadrature outputs.

An optimized ΔΣ fractional-N frequency synthesizer for CMOS UHF RFID reader

A novel 3-bit 3rd-order ΔΣ fractional-N frequency synthesizer specialized for monolithic UHF band radio frequency identification reader is implemented in 0.18µm CMOS technology. The phase noise requirements are recapitulated for the zero-IF transceiver architecture and EPC global C1G2 and ETSI multi-protocol operation. The measurement results show that the synthesizer phase noise at 200 kHz offset is suppressed by the additional zero configuration in delta-sigma modulator (DSM)s noise transfer function with acceptable in-band noise penalty. The measured phase noise is −102 and −126.5dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz operation frequency while drawing 9.6 mA from 1.8 V power supply. 1

A silicon BiCMOS single-chip UHF receiver design

A single-chip UHF receiver integrated with PLL working at ISM band from 290 MHz to 470 MHz is presented. It operates from a single 5 V supply with a nominal current consumption of only 6.5 mA (with all parts of the receiver are active). The IC requires only a low frequency reference clock (crystal oscillator), a varactor diode, and a few standard passive elements to operate fully, satisfying almost all of the low power radio regulations. The LNA has a 1.56 dB noise figure, 15.2 dB power gain and 8 dBm IIP3. The mixer has a 9.3 dB SSB noise figure with 5 dBm IIP3. The PLL achieves a phase noise of -99.7 dBc/Hz at 100 kHz offset with 433 MHz carrier frequency. The RF receiver was implemented in a 0.8 /spl mu/m, 12 GHz f/sub T/ (NPN) Si BiCMOS production technology.

A novel blocker rejection receiver front-end for single-chip UHF RFID Reader

A blocker rejection receiver front-end for 840-960 MHz single-chip UHF RFID Reader is presented in this paper. The proposed receiver front-end injects the blocker replica signal into the differential LNA of RF front-end, through a feedback path to actively create a narrowband notch filtration for the self-jammer and not affect the gain for the backscattered tag signal. In contrast to the traditional feedforward technique, the loop selectivity does not depend on the precise gain matching of two paths but on the open loop gain which is easier to obtain. The receiver front-end is fabricated in 0.18 μm CMOS process and draws 36 mA from 3.3 V power supply. In the talk mode, tag signal gain merely drops by 1 dB for a +10 dBm self-jammer when the feedback blocker rejection being enabled.