Zongsheng Lai

Energy and thermal aware mapping for mesh-based NoC architectures using multi-objective ant colony algorithm

Where IP cores to be mapped must be carefully solved for any given application in order to optimize different performance metrics in Network-on-Chip (NoC) design flow. The optimization of different performance metrics simultaneously may cause a negative effect on each other because of the strong correlation between these performance metrics. In this paper, we propose a multi-objective ant colony algorithm (MOACA) that maps IP cores onto mesh-based NoC architectures. This algorithm is an efficient way to find the pareto-optimal front which optimizes energy consumption and hotspot temperature of NoC. The algorithm has been implemented and evaluated for synthetic generated benchmarks. Experimental results confirm the efficiency, accuracy and scalability of the algorithm.

A novel tunable low-pass filter based on MEMS and CPW

This paper presents a new type of tunable low-pass filter for millimeter-waves. The filter is based on the slow-wave coplanar waveguide (CPW) lines and tuned by the MEMS capacitive shunt switches. There are 5 switches which can provide two orders of tunable mode. In the first order tuning, the 3dB cut-off frequency changes from 8.2GHz to 10.5GHz, and the second order tuning is 8.2GHz to 16.8GHz. The tested results show that the pass-band ripple is less than 2dB and the maximal out-of-band rejection is better than 20dB. The driven voltages of the switches are around 40V.

An multi-rate LDPC decoder based on ASIP for DMB-TH

Based on ASIP (Application Specific Instruction Set Processor), this paper propose a decoder architecture for LDPC (Low Density Parity Check Codes) in the DMB-TH standard. The decoder use a five-stage pipeline, 32-bit RISC processor and it can supports three different code rates (0.4, 0.6 and 0.8) by only modifying the program. Based on XC4VLX150, at the max frequency of 126 MHz, the max throughput of the decoder can achieve 96Mps for 10 TDMP-decoding Iterations. Compared with other GPP and DSP implementations, this ASIP simplify the control logical and enhance the flexibility1.

Characterization of micromechanical optical modulator

In this paper, a Fabry-Perot optical modulator fabricated by surface micromechanical technique is presented. The modulator is optimized for a wavelength of 1.3 /spl mu/m and is intended for a fiber-to-the-home system. The actuation voltage of the modulator is measured to be 10-25 V. The optical modulator has a series of resonant frequencies determined from the device structure. When the modulator is driven by a sinusoidal signal, the output frequency will be doubled. For a driving signal greater than a certain value, the oscillation amplitude of the membrane will exceed /spl lambda//4, resulting in an ultrasaturation phenomenon.

A single-chip CMOS UHF RFID reader transceiver

UHF RFID reader transceiver for Chinese local standard (840-845 MHz and 920-925 MHz), in concord with the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C, is presented. A highly linear RF front-end with low flicker noise, an on-chip self-jammer cancellation (SC) circuit with fast time-varying cut-off frequency and a DC-offset cancellation (DCOC) circuit are proposed to deal with the large self-jammer in the receiver. In the presence of 22 dBm PA output power, the receiver achieves a sensitivity of -79 dBm including the 15 dB loss of the directional coupler. A CMOS class-AB PA is integrated in the transmitter, with 22 dBm output power and 35% PAE. The spectrum mask achieves ACPR1 of -45 dBc and ACPR2 of -60 dBc . A sigma-delta fractional-N PLL with a single LC VCO is also implemented for good phase noise (-126 dBc/Hz @ 1 MHz offset) and high frequency resolution within 1 kHz. This single-chip is fabricated in a 0.18 standard CMOS process. It occupies a silicon area of 13.5 mm2 and dissipates 203 mW from a 1.8 V supply voltage when transmitting 7.5 dBm output power.

Uniform All-Integer Quantization for Irregular LDPC Decoder

In this paper, we present a uniform all-integer quantization for irregular LDPC decoder. The LLR values at the variable nodes and the check nodes are mapped to integer with their integer part of their value directly. Variable nodes are quantized to 6-bit integer and check nodes are quantized to 4-bit integer after the input channel messages are scaled up, and at a given iteration number the messages are scaled down. A lookup table is used to store the configuration parameters for quantization, and the hardware architecture of quantization is proposed. Simulations of (3048,7493) show the performance is better than the floating point in normalized min-sum and close to floating point in offset min-sum. The uniform all-integer quantization is easy to be implemented and does not require the floating point operations and so reduces the hardware complexity and lower power.

Compound sacrificial layer process for RF MEMS applications

Compound sacrificial layer has been developed for RF membrane bridge switch in micro electro mechanical systems (MEMS) tunable filters. The compound sacrificial layer consisting of polyimide and positive photoresist is used to avoid drawbacks which will occur when only polyimide or positive photoresist is used as sacrificial layer for suspended membrane with large area. The wet etching and dry etching are used to remove positive photoresist and polyimide, respectively. And the results of baking and etching of sacrificial layer are improved. The time is also shortened for the complete removal of sacrificial layer.

A 0.8–2.5GHz wideband SiGe BiCMOS low noise amplifier with noise fiugre of 1.98–3.3dB

This paper presents an optimized 0.8–2.5GHz low noise amplifier for wideband applications. Based on cascade structure, a shunt resistive feedback with an emitter degeneration inductor is used. Both low noise figure and high gain are achieved simultaneously. Measured results show that the proposed LNA has a maximum gain of 19.6dB at 0.8GHz and a minimum gain of 14.3dB at 2.5GHz. The noise figure varies from 1.98 to 3.3dB among the whole band. The overall power supply is 24mw at 3V supply and the occupied die area is only 0.4mm2.

ASIC design of UHF RFID reader digital baseband

This paper presents the ASIC design and implementation of digital baseband system for UHF RFID reader based on EPC Global C1G2 /ISO 18000–6c protocol. The digital baseband system consists of two parts: transmitter and receiver, which inculing encoding module, decoding module, channel fllers, CRC chenk module, control module and a SPI module. It is described in verilog HDL in RTL level, with Design Compiler for synthesizing, PT for static timing analyzing and Astro for physical design. The die is fabricated using IBM 130nm 8-layer-metal RF cmos process successfully, which size is 3 mm × 3mm, the power consumption is around 6.7mW. It can be applied in the research of single-chip UHF RFID reader.

A Stack-Mode Dual-Band Voltage-Controlled Oscillator for Multistandard Wireless Applications

A stack-mode dual-band VCO, which can be applied to 802.11a/b/g and Bluetooth multi-standard zero-IF transceiver, is proposed with low power consumption of 12.22 mW and excellent phase noise performance of -126.2 and -120.1 dBc/Hz at 1MHz offset from 2.44 and 5.23 GHz carriers. The simulation is performed in Agilent ADS and this circuit with chip area of 1.18times0.67 mm2 will be implemented by 0.18-mum CMOS process