Cicero S. Vaucher

A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.

An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.

A wide-band tuning system for fully integrated satellite receivers

The building blocks for a low power tuning system that reduces the phase noise of integrated VCOs are described. The multi-modulus prescaler, the phase frequency detector and the wide band charge pump were integrated in a standard bipolar technology with 9 GHz npn-transistors and 200 MHz pnp-transistors. The maximum input frequency of the multi-modulus prescaler is 3 GHz, the maximum reference frequency of the phase frequency detector is 380 MHz and the -3 dB bandwidth of the charge pump is 41 MHz at a reference frequency of 300 MHz. The achieved performance enables use of noisy integrated VCOs for reception of satellite digital signals.

Architectures for RF frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products. Written for: Electrical and electronic engineers

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-/spl mu/m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-/spl mu/m CMOS

A low-power fully integrated synthesizer for Bluetooth applications is presented. The circuit with quadrature output signals at 2.45 GHz and 15-mW power dissipation has been designed in a digital 0.18-/spl mu/m CMOS process with 1.8-V supply voltage. The only external component is a 64-MHz crystal. Measurements have been performed on packaged samples mounted on an FR-4 board and show that the Bluetooth requirements are met. The measured phase noise is below -120 dBc/Hz at 3-MHz offset, and the resulting residual frequency modulation is 7.4-kHz rms. The tuning range consists of an analog and digital tuning mechanism, resulting in more than 15% overall tuning range.

A low-power 20 GHz static frequency divider with programmable input sensitivity

A low-power frequency divider (divide-by-8) is described which operates up to frequencies in excess of 20 GHz with a supply voltage of 2.7 V. The circuit is implemented in a standard bipolar Silicon technology with a maximum f/sub T/ of 37 GHz. The total power dissipation is 57 mW, with 11 mW dissipated in the first divider stage. An innovative implementation of a Toggle flip-flop enables the input sensitivity to be adapted as a function of the input frequency, extending the operation range with respect to standard techniques. An AC simulation model for evaluation of the high frequency performance as a function of design parameters is introduced.

Low-cost silicon-germanium ICs for digital satellite outdoor units

Low-cost IC for consumer digital satellite outdoor units are described. The receiver IC includes a mixer and a fully integrated PLL frequency synthesizer, eliminating manual alignment. The transmitter IC is a PLL building block for satellite return channel up-converters.

Tuning system for low voltage zero-IF digital satellite receivers

A new tuning system is described that reduces the phase noise of fully integrated, low tuning voltage VCOs. Zero-IF receivers employing this tuning system architecture do not suffer from typical zero-IF problems. It enables a better RF performance, a robust receiver design and an easier RF application.