Melina Apostolidou

A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off

A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in a baseline 65 nm CMOS technology. The PA is constructed as a cascode stage formed by a standard thin-oxide device and a dedicated novel high voltage extended-drain thick-oxide device. Both devices are implemented without using additional masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off. Stress tests indicate the reliability of both the novel high voltage device and the design.

A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency

A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in 65 nm CMOS technology. The PA is a cascode stage formed by a standard thin-oxide device and a high voltage extended-drain thick-oxide device. Both devices are implemented in a standard sub-micron CMOS technology without using extra masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off.

Wideband UHF ISM-band transceiver supporting multichannel reception and DSSS modulation

Wireless car keys, tire pressure sensors and wireless car diagnostic systems operate in the UHF ISM-bands using FSK/GFSK or ASK/OOK modulation with data rates between 0.5 and 200Kb/s. Recently, long-range car key applications have become popular, requiring the support of longer radio links within the boundaries of legislation and battery life. BPSK DSSS modulation allows increasing the transmitter power without violating legislation on maximum transmitted power density, but at the cost of having a non-constant RF signal envelope and a larger signal bandwidth. Unfortunately both these properties are not supported by classical narrow-band FSK/ASK transceivers.

A 65nm CMOS pulse-width-controlled driver with 8V pp output voltage for switch-mode RF PAs up to 3.6GHz

State-of-the-art wireless communication radios are implemented in deep-submi-cron CMOS, including the RF power amplifiers (PAs). However, in wireless infrastructure systems, the RF PA is often realized in an LDMOS or a compound technology to obtain the required large output powers. For next-generation reconfigurable infrastructure systems, the switch-mode PAs (SMPA) seem to offer the required flexibility for multiband multimode transmitters. In order to interface the high-power devices of the SMPA with the digital CMOS blocks of the transmitter, a wideband RF CMOS driver capable to generate high voltage (HV) swings is required. In this way, digital signal processing can be directly applied to control the required input pulse shapes of the SMPA.

Scalable CMOS power devices with 70% PAE and 1, 2 and 3.4 Watt output power at 2GHz

This paper reports RF power devices achieving 70% power-added efficiency (PAE) with 1, 2 and 3.4W output power at 2GHz. The power devices operate as sub-optimum class-E power amplifiers, having the advantage of 1.6 times higher output power with a slightly lower PAE than conventional class-E. The power devices use high voltage extended-drain NMOS (ED-NMOS) transistors in standard 65nm CMOS. A scalable layout design that we used preserves the high PAE for the various output power levels.

Wideband and efficient watt-level SiGe BiCMOS switching mode power amplifier using continuous class-E modes theory

In this paper, a generic, wide-band switch mode power amplifier (SMPA) design approach is developed based on the continuous class-E modes theory. A watt level, 1.3-2.2 GHz SiGe BiCMOS class-E SMPA is realized for experimental verification. The prototype provides collector efficiencies higher than 70% and output power levels higher than 29 dBm across 1.3-2.2 GHz band, fully confirming the validity of the proposed design approach.

A 550–1050MHz +30dBm class-E power amplifier in 65nm CMOS

A 65nm CMOS broadband two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To reduce the peak drain-source voltage and improve reliable operation, sub-optimum class-E operation is applied. The PA is followed by a broadband output matching network implemented as an off-chip two-stage LC ladder. The measurements with a 5.0V supply voltage for the power stage and 2.4V for the driver stage show a drain efficiency > 67% and a power-added efficiency (PAE) > 52% with a Pout > 30dBm within 550MHz–1050MHz. The output power variation is within 1.0dB and efficiency variation is less than 13%. The highest efficiency is observed at 700MHz with peak drain efficiency of 77% and peak PAE of 65% at a Pout of 31dBm and 17dB power gain. By using dynamic supply modulation, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off from 30dBm.

Generalized Semi-Analytical Design Methodology of Class-E Outphasing Power Amplifier

This paper presents a time domain generalized semi-analytical solution for the class-E outphasing power amplifier (OPA). Instead of assuming ideal voltage sources for active devices, the proposed class-E OPA model obtains the circuit elements by analytically solving the class-E equations for two mutually loaded active devices and numerical optimization. The analysis takes into account the dc-feed inductor, duty-cycle, switch resistances and the class-E conditions at certain outphasing angle. Three different topologies are deduced from the proposed generalized model. The design equations for the circuit elements are derived analytically using the given class-E conditions. The overall outphasing performance is obtained numerically, and the optimum design settings are determined by the desired output power and efficiency characteristics. It will be shown that the proposed class-E OPAs can ideally maintain high efficiency ( >80%) at 12-dB power back-off with a static square-wave drive signal. With 5-MHz UMTS downlink signal, the ideal average efficiency is more than 80%. The spectral and modulation requirements are satisfied when the predistortion is applied to the class-E OPA.

Phase noise in frequency divider circuits

We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results.