Cindy Yuen

High-gain, low-noise monolithic HEMT distributed amplifiers up to 60 GHz

Ultrabroad-bandwidth distributed amplifiers with cutoff frequencies of 45 to 60 GHz were developed using 0.25- mu m high-electron-mobility transistors (HEMTs) with a mushroom gate profile. Both single and cascode HEMTs were used as the active devices in the amplifiers. A measured gain as high as 10+or-1 dB from 5 to 50 GHz and a gain of 8+or-1 dB from 5 to 60 GHz, respectively, were achieved from amplifiers using cascode HEMTs. The measured noise figure for these amplifiers is approximately 3-4 dB in the Ka-band. The chip size is 2.3*0.9 mm. Device considerations, circuit design, monolithic IC fabrication, and the measured performance of the amplifiers are outlined.<<ETX>>

A 2-20 GHz, High-Gain, Monolithic HEMT Distributed Amplifier

A low-noise 2-20 GHz monolithic distributed amplifier utilizing 0.3-micron gate-length HEMT devices has achieved 11-dB +- 0.5 dB of gain. This represents the highest gain reported for a distributed amplifier using single FET gain cells. A record low noise figure of 3 dB was achieved mid-band (7-12 GHz). The circuit design utilizes five HEMT transistors of varying width with gates fabricated by E-beam lithography.

A monolithic 40-GHz HEMT low-noise amplifier

A description is given of a monolithic, reactively matched 40-GHz low-noise amplifier using a 0.25- mu m high-electron-mobility transistor (HEMT) as the active device. Standard processing techniques were used for most of the fabrication steps. An amplifier using a triangular gate profile achieved approximately 6.5-dB gain and a 5-dB noise figure from 38 to 44 GHz. The gain of the amplifier increased to 8 dB and the noise figure decreased to 4 dB when the gate was replaced by one with a mushroom-like profile. The chip size is 1.1 mm*1.1 mm.<<ETX>>A monolithic, single-stage HEMT (high-electron-mobility transistor) low-noise amplifier has been developed at 40 GHz. This amplifier includes a single 0.25- mu m gate-length HEMT active device with on-chip matching and biasing circuits. A gain of 6.5 dB and a noise figure of 5 dB were measured from 38 to 44 GHz. By replacing the triangular gate profile with a mushroom gate profile the amplifier achieved 8-db gain and 4-dB noise figure from 36 to 42 GHz. The chip size is 1.1 mm*1.1 mm.<<ETX>>

50 GHz high output voltage distributed amplifiers for 40 Gb/s EO modulator driver application

Both single-ended and differential distributed amplifiers were developed using 0.15 /spl mu/m GaAs power PHEMT for 40 Gb/s EO modulator driver circuits. The single-ended approach has achieved 12 dB gain up to 50 GHz, greater than 5 dB gain control range and output voltage >6.5 Vp-p measured at 10 Gb/s. Power transfer data shows Psat of 20 dBm at 40 GHz, which translates to 6.3 Vp-p swing at 40 GHz. The differential approach has achieved 8 dB gain up to 45 GHz and differential output voltage of 9 Vp-p measured at 10 Gb/s. These amplifiers are suitable for use In fiber-optic communication systems.

A monolithic Ka-band HEMT low-noise amplifier

A monolithic, single-stage high-electron-mobility transistor (HEMT) low-noise amplifier was developed for the 20-40-GHz band. This amplifier includes a single 0.25- mu m-gate-length HEMT active device with on-chip matching and biasing circuits. A gain of approximately 6 dB from 20 to 38 GHz and a noise figure of approximately 5 dB from 26.5 to 38 GHz were measured. The chip size is 2.2 mm*1.1 mm.<<ETX>>

A compact flip chip single die WiFi FEM for smart phone application

A flip chip single die WiFi FEM is developed using Bi-FET (HBT+E/D-PHEMT) technology for smart phone application. High thermal conductive copper-pillar bumps were developed for the flip chip process. This FEM flip chip die consists of a high-pass filter (HPF), a 2GHz WiFi PA with on-chip regulator, PAON logic and detector circuit, and an SP3T. It showed good over-voltage and over-temperature performance when mounted on test LTCC module. Thermal modeling and design optimization kept junction temperatures comparable to wirebond versions of the design. A complete WiFi front-end LTCC module was developed using flip chip FEIC, integrated balun and SAW filter, with 3.2mmx3.2mm size for Smart Phone Application.

Single chip RF front-end MMIC solutions for future low cost, miniature size, WLAN transceiver module applications

Several highly integrated RF front-end modules (FEMs) for 802.11 b/g and a/b/g applications are described. In a single 4/spl times/4 mm or 5/spl times/5 mm QFN package, these FEMs include linearized power amplifier(s), a low-noise amplifier, T/R diversity switch, filters, diplexers, power detectors, and all biasing and matching circuitry. The RF FEMs replace over 30 discrete and IC components with a single package, and require practically no external components. They have the smallest footprint of any 802.11 FEM on the market and allow significant cost savings at the system level by reducing parts count, simplifying assembly, and increasing yield.

High Level Integrated ICs for Low Cost, Compact, WiMax Dual-band RF Modules

High level integrated passive and active ICs on GaAs substrates are developed for low cost, compact size WiMax dual-band RF module applications.

Via hole studies on a monolithic 2-20 GHz distributed amplifier

The effect of source inductance on the performance of a distributed amplifier is investigated. A simple theoretical analysis shows that optimum performance is obtained with as low a source inductance as possible (as would be intuitively expected), and that the flattest gain and minimum gate line attenuation occur with the inductance common to the whole amplifier rather than parceled out to each FET individually, as would occur for a MIC distributed amplifier. A novel through-the-wafer via hole process has been developed for a low-inductance contact on monolithic circuits. A 2-20 GHz variable-gate-width monolithic distributed amplifier fabricated with this via-hole grounding technique has demonstrated a 2-dB gain improvement as well as a flatter gain profile compared to that without via grounding. Evidence is presented that indicates that MMIC (monolithic microwave integrated circuit) designs may not be as ideal as expected with regard to being typified by the common inductance case. >

Thermal optimization of a flip-chip WiFi RF front-end IC

Flip-chip designs offer several advantages over traditional designs. However, thermal characteristics must be considered carefully, or the end result may have high junction temperatures and thus poor performance and poor reliability. This paper presents some guidelines for thermal optimization in flip-chip designs, and presents the results of a flip-chip single die WiFi FEM developed using Bi-FET (HBT+E/D-PHEMT) technology. In this design, both solder bumps and copper pillar bumps were developed for the flip chip process.