Clarence Tracy

Surface passivation of n-type c-Si wafers by a-Si/SiO2/SiNx stack with <1 cm/s effective surface recombination velocity

The passivation quality of an a-Si/SiO2/SiNx (aSON) stack deposited by conventional PECVD at 60 ms on 5000 Ω-cm and 20.9 ms on 1.7 Ω-cm mirror polished float zone (FZ) material passivated with aSON stacks.

Explanation of the device operation principle of amorphous silicon/ crystalline silicon heterojunction solar cell and role of the inversion of crystalline silicon surface

The device operation principle of amorphous silicon/crystalline silicon heterojunction solar cell is discussed. The band diagram obtained by the computer model developed in the commercial simulator Sentaurus shows that the c-Si surface is inverted at the interface between a-Si and c-Si (heterointerface). A strong inversion gives a strong electric field at the c-Si surface, which in turn facilitates the transport of minority carriers across the heterointerface. A high performance device requires a strongly inverted c-Si surface. Calculations are performed to show that the doping of the doped a-Si layer, the thickness of the intrinsic layer, and the defect state density at the heterointerface all affect the inversion of the crystalline silicon surface. Unlike homojunction devices, the defects in heterojunction devices have a greater role in transport mechanism than in recombination mechanism. The results show that in devices with a large number of defects at the interface, the fill factor degrades with little change in open circuit voltage. This explains why it is relatively easy to obtain VOCs approaching 700 mV with heterojunctions but often with low fill factors.

Manipulation of K center charge states in silicon nitride films to achieve excellent surface passivation for silicon solar cells

High quality surface passivation (Seff  ±8 × 1012 cm−2) into a dual layer stack of Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon Nitride (SiNx)/PECVD Silicon Oxide (SiO2) films using a corona charging tool. We demonstrate long term stability and uniform charge distribution in the SiNx film by manipulating the charge on K center defects while negating the requirement of a high temperature thermal oxide step.

A study of platinum electrode patterning in a reactive ion etcher

This article addresses the problem of Pt electrode etching through the use of a batch load production reactive ion etch (RIE) tool to study etching characteristics and the cleanliness of patterned films with pressure, total gas flow, and percent of Cl2 in Ar as variables, and considers some of the environmental, health, and safety issues. The results show that Pt etching is primarily a sputter etch process in which the Cl2 percentage has little impact on the Pt removal rate, but does significantly affect etch uniformity across the wafer and the surface cleanliness as analyzed with Auger electron spectroscopy. The maximum Pt etch rate achieved was about 5 nm/min with good etch uniformity and surface cleanliness. X-ray photoelectron spectroscopy of the etch by-products shows the presence of PtCl2 and PtCl4 when the Ar–Cl2 etch chemistry was used. These results provide useful information to address material redeposition, wafer cleaning, and etch chamber cleaning safety issues, major concerns in the RIE of Pt.

A simplified process flow for silicon heterojunction interdigitated back contact solar cells: Using shadow masks and tunnel junctions

A novel process flow, which can allow the formation of interdigitated p- and n-type a-Si strips and corresponding transparent conductive oxide (TCO) and metal layers for silicon heterojunction interdigitated back contact (SHJ-IBC) solar cells using only a single alignment step and without using any resist patterning is presented. The flow is based on the deposition of a-Si, TCO and metal layers through a stack of shadow masks. Three variation of the flow are described. Several key process components to include a-Si deposition and H2 plasma etch through the shadow mask are demonstrated and described.

Electroplated Al as the front electrode in crystalline-Si solar cells

This paper reports aluminum (Al) electroplating as the metallization technique for the front finger electrode on n-type silicon (Si) in crystalline-Si solar cells. The development of the Al electroplating process is motivated by the limited reserves of silver (Ag) on this planet and the industry-wide push to reduce Ag usage for cost control. The new metallization process consists of: (1) patterning the silicon nitride (SiNx) layer for front electrode; (2) depositing a nickel (Ni) seed layer into the opening; (3) electroplating self-aligned Al onto the Ni seed layer and (4) annealing the Al/Ni electrode in air at ~200°C. This temperature is far below the typical firing temperatures for commercial Al pastes. The new metallization process has been integrated into commercial p-type monocrystalline Si solar cells from Hareon Solar. An all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al back electrode, has been demonstrated. The cell has a size of 2.54×2.54 cm2, with efficiencies approaching 15% demonstrated.

Non-vacuum electroplated al for n-side electrode in Si solar cells

This paper reports Al electroplating on a Si substrate using a room-temperature ionic liquid for the metallization of Si solar cells. The ionic liquid electrolyte was prepared by mixing anhydrous AlCl3 and 1-ethyl-3-methylimidazolium tetrachloroaluminate ([EMIM]AlCl4). The plating process was carried out in a dry nitrogen box. A sacrificial Al anode was employed, making the electrolyte reusable for many deposition runs. The sheet resistance of the Al deposits was investigated to reveal the effects of pre-bake conditions, deposition temperature, and post-deposition annealing conditions. It was found that dense and adherent Al deposits with low electrical resistivity can be obtained directly on Si substrates over a wide range of temperatures using galvanostic deposition. The resistivity of the Al deposits was in the high 10-6 Ω-cm range, similar to that of screen-printed Ag. The maximum process temperature for electroplated Al was 350°C. An all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al back electrode, has been demonstrated, and its optimization and characterization will be reported soon.

Study and manipulation of charges present in silicon nitride films

As crystalline silicon solar cells continue to get thinner, the surfaces of the cell play an ever important role in controlling the cell efficiency. One tool to minimize surface recombination is field effect passivation from the charges present in the thin films applied on the cell surfaces. Basic PC 1D simulations were carried to understand the relation between the amount and sign of charge on cell efficiencies with varying emitter-doping levels. Silicon nitride (SiNx) thin films are known to carry net positive fixed charges that originate from specific silicon nitrogen dangling bonds (*SiN3) known as K centers. The properties of fixed positive charges present in as-deposited SiNx films are studied by capacitance - voltage (CV) and electron spin resonance (ESR) techniques. We report that the as-deposited SiNx films also carry neutral defects (K0 centers) that can easily be manipulated to either positive (K+) or negative (K) charge states depending on the end application. Corona charging was used to change the net charge in the film to either positive or negative and high energy (sub-300 nm) UV light was used to neutralize or annihilate the charges. ESR measurements showed that the neutral K0 defects are distributed throughout the bulk of the nitride film. A high temperature annealing step decreases the amount of neutral defects possibly due to bonding of hydrogen with the K center. First order effects of both positive and negative nitride charges on test structures were studied by photoconductance measurements.

Experimental and theoretical verification of the presence of inversion region in a-Si/c-Si heterojunction solar cells with an intrinsic layer

Photovoltaic devices based on amorphous silicon (a-Si)/ crystalline silicon (c-Si) heterostructure exhibits excellent surface passivation with the highest open circuit voltage being reported on these devices. A plausible explanation for these devices to show low recombination is that the junction is induced in c-Si and an inversion region is present at the heterointerface. In this work, the presence of the inversion region at the heterointerface between intrinsic a-Si and c-Si is theoretically shown by a computer model developed in the commercial simulator Sentaurus and experimentally corroborated by lateral conductance measurement technique.

Vertically grown Ge nanowire Schottky diodes on Si and Ge substrates

The processing and performance of Schottky diodes formed from arrays of vertical Ge nanowires (NWs) grown on Ge and Si substrates are reported. The goal of this work is to investigate CMOS compatible processes for integrating NWs as components of vertically scaled integrated circuits, and elucidate transport in vertical Schottky NWs. Vertical phosphorus (P) doped Ge NWs were grown using vapor-liquid-solid epitaxy, and nickel (Ni)-Ge Schottky contacts were made to the tops of the NWs. Current-voltage (I-V) characteristics were measured for variable ranges of NW diameters and numbers of nanowires in the arrays, and the I-V characteristics were fit using modified thermionic emission theory to extract the barrier height and ideality factor. As grown NWs did not show rectifying behavior due to the presence of heavy P side-wall doping during growth, resulting in a tunnel contact. After sidewall etching using a dilute peroxide solution, rectifying behavior was obtained. Schottky barrier heights of 0.3–0.4 V and ...