Clark D. Thompson

Sorting on a mesh-connected parallel computer

Two algorithms are presented for sorting n2 elements on an n × n mesh-connected processor array that require O (n) routing and comparison steps. The best previous algoritmhm takes time O(n log n). The algorithms of this paper are shown to be optimal in time within small constant factors. Extensions to higher-dimensional arrays are also given.

Area-time complexity for VLSI

The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points (N) in the DFT: AT<supscrpt>2</supscrpt>≥ N<supscrpt>2</supscrpt>/16. This inequality holds for any chip design based on any algorithm, and is nearly tight when T &equil; <italic>&thgr;</italic>(N<supscrpt>1/2</supscrpt>) or T &equil; <italic>&thgr;</italic>(log N). A more general lower bound is also derived: AT<supscrpt>x</supscrpt> &equil; Ω(N<supscrpt>1+x/2</supscrpt>), for 0≤×≤2.

On the Average Number of Maxima in a Set of Vectors and Applications

A maximal vector of a set ~s one which is not less than any other vector m all components We derive a recurrence relation for computing the average number of maxunal vectors m a set of n vectors m d-space under the assumpUon that all (nl) a relative ordermgs are equally probable. Solving the recurrence shows that the average number of maxmaa is O((ln n) a-~) for fixed d We use this result to construct an algorithm for finding all the maxima that have expected running tmae hnear m n (for sets of vectors drawn under our assumptions) We then use the result to find an upper bound on the expected number of convex hull points m a random point set

Area-time optimal adder design

A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS. >

Provably good routing in graphs: regular arrays

We examine the problem of routing wires on a VLSI chip where the nodes to be connected are arranged in a two-dimensional array. We develop provably good algorithms that find a solution close to the optimal one with high probability. Our approximation algorithms solve the relevant 0-1 integer optimization problems by solving their relaxed versions and then rounding by an interesting probabilistic technique. One of our algorithms, using multicommodity flow, has applications to routing in circuit switching networks.

Multiterminal global routing: A deterministic approximation scheme

We consider the problem of routing multiterminal nets in a two-dimensional gate-array. Given a gate-array and a set of nets to be routed, we wish to find a routing that uses as little channel space as possible. We present a deterministic approximation algorithm that uses close to the minimum possible channel space. We cast the routing problem as a new form of zero-one multicommodity flow, an integer-programming problem. We solve this integer program approximately by first solving its linear-program relaxation and then rounding any fractions that appear in the solution to the linear program. The running time of the rounding algorithm is exponential in the number of terminals in a net but polynomial in the number of nets and the size of the array. The algorithm is thus best suited to cases where the number of terminals on each net is small.

A Minimum-Area Circuit for l-Selection

We prove tight upper and lower bounds on the area of semelective, when-oblivious VLSI circuits for the problem ofl-selection. The area required to select thelth smallest ofnk-bit integers is found to be heavily dependent on the relative sizes ofl,k, andn. Whenl<2k, the minimal area isA = Θ(minn,l(k-logl)). Whenl≥2k,A = Θ(2k(logl-k + 1)).