Claude Milan

Implementation of a real time image rotation using B-spline interpolation on FPGA's board

The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGAs board. The method we used is based on M. Unsers work (1993) and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem, we have searched for determining the minimum number of bits to code the filter while keeping a good accuracy on filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B-spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in order to determine the filter data coding.The aim of our work is to realize the implementation of a real-time image rotation on FPGAs board. The method we used is based on a B-spline interpolator. The integration capicity of FPGAs is relatively weak, so the difficulty in this problem is to determine the right coding of the rotation filter while keeping a good accuracy on filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B-spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in order to determine the filter data coding.

Real Time Image Rotation Using Dynamic Reconfiguration

Abstract Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and performance. It appears that, according to the nature of the application, the dynamic reconfiguration can be less or more advantageous. In order to be able to test the validity of our approach in terms of algorithm and architecture adequacy, we realized an AT40K40-based board “ARDOISE”.

A high-speed video microsystem

This paper describes a complete fast imaging microsystem for biological applications. The main goal of this microsystem is to provide, at a very low cost, a high-speed camera with an associated storage data system. We attained this goal by using a standard area CCD image sensor connected to a PC-compatible computer.

High-speed cameras using a CCD image sensor and a new high-speed image sensor for biological applications

This paper describes two complete fast imaging systems using a commercial Charge Coupled Device (CCD). It includes two different storage systems (analogical and digital) and describes a new high speed sensor built as an Application Specific Integrated Circuit (ASIC) in Complementary Metal Oxide Semiconductor (CMOS) 1.2 micrometers technology. The first system has been applied to a biological research.

Real-time image rotation on FPGA's board

The aim of this work is to realize the implementation of real-time high-quality image rotation on an FPGA board. The method we use is based on the work of Unser et al. (1993) and consists in applying a B-spline interpolator. The difficulty of this problem is due to the large number of operations needed to implement this solution on FPGAs which have a relatively weak integration capacity. To solve this problem, we have searched for a way of determining the minimum number of bits to code the filter while keeping good accuracy on the filtering output. In this article, we briefly review B-spline function definitions and present how we use B-spline interpolation for the image rotation problem. We then describe the way we calculate the probability density function of the output error in order to determine the filter data coding.

Achieving high performances at lower cost for real-time image rotation by using dynamic reconfiguration

FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGAs dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy , we realized an AT40K40 based board ARDOISE.

Real time image rotation using B-spline interpolation on FPGA's board

The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGAs board. The method we used is based on M. Unsers work and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem we have searched for determining the minimum number of bits to code the filter while keeping a good accuracy of filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B- spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in order to determine the filter data coding.

New high-speed camera and real-time compression

This article describes the present development of a complete fast imaging microsystem, which the main aim is to propose, for biological applications and with a low cost, a high speed camera (2400 frames per second) and its data storage system associated. This microsystem uses a multiple parallel outputs CCD image sensor and will be connected to a PC computer compatible.

Parallel implementation of a multiscale edges detection algorithm

We present in this paper an implementation of a multiscale edges detection algorithm on multiprocessor using SYnDEx which is a programming environment to generate optimized distributed real-time executives. The implementation has been done on three TMS320C40 and the acceleration in comparison with one processor is 2.2.