Claudia Feregrino

Hardware-software platform for computing irreducible testors

In pattern recognition, feature selection is a very important task for supervised classification. The problem consists in, given a dataset where each object is described by a set of features, finding a subset of the original features such that a classifier that runs on data containing only these features would reach high classification accuracy. A useful way to find this subset of the original features is through testor theory. A testor is defined as a subset of the original features that allows differentiating objects from different classes. Testors are very useful particularly when object descriptions contain both numeric and non-numeric features. Computing testors for feature selection is a very complex problem due to exponential complexity, with respect to the number of features, of algorithms based on testor theory. Hardware implementation of testor computing algorithms helps to improve their performance taking advantage of parallel processing for verifying if a feature subset is a testor in a single clock cycle. This paper introduces an efficient hardware-software platform for computing irreducible testors for feature selection in pattern recognition. Results of implementing the proposed platform using a FPGA-based prototyping board are presented and discussed.

On the design and implementation of a high performance configurable architecture for testor identification

Typical testors are a useful tool to do feature selection in supervised classification problems with mixed incomplete data. However, the complexity of computing all typical testors of a training matrix has an exponential growth with respect to the number of columns in the matrix. For this reason different approaches like heuristic algorithms, parallel and distributed processing, have been developed. In this paper, we present a configurable custom architecture for the efficient identification of testors from a given input matrix. The architectural design is based on a brute force approach that is suitable for high populated input matrixes. The architecture has been designed to deal with parallel processing and can be configured for any size of matrix. The architecture is able to evaluate if a vector is a testor of the matrix in a single clock cycle. The architecture has been implemented on a Field Programmable Gate Array (FPGA) device. Results show that it provides runtime improvements over software implementations running on state-of-the-art processors. FPGA implementation results are presented and implications to the field of pattern recognition discussed.

FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding

This paper presents a hardware implementation of an adaptive modelling unit for parallel binary arithmetic coding. The presented model combines the advantages of binary arithmetic coding where the coding process is simplified, with the benefits of multi-alphabet arithmetic coding where any type of data can be compressed. The modelling unit adopts a simple method to store and modify the information, making it able to process 8 bits per clock cycle and to increase substantially the arithmetic coding speed. This model has been implemented in an A500K130 ProASIC FPGA and offers a throughput of 256 Mbits/s.

The X-MatchLITE FPGA-based data compressor

This paper describes a high speed VHDL implementation of a polynomial division algorithm suitable for FPGA implementation. Examples & benchmarks will be shown for an ITU-T I.363 compliant CRC-32 implementation with data throughput in excess of 3 Gbits/sec bits, based on processing 32 bit words. The VHDL code is parameterized, accepting a static polynomial of arbitrary length, and an input data word of arbitrary width. A parity matrix is calculated during elaboration of the VHDL that specifies the XOR gate size and connections required for implementation of the polynomial divider circuit. URL: http://www.mhnk.net/-jqrn/crc.pdf

X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor

This paper presents the full-duplex architecture of the X-MatchPRO lossless data compressor and its highly integrated implementation in a non-volatile reprogrammable ProASIC FPGA. The X-MatchPRO architecture offers a data independent throughput of 100 Mbytes/s and simultaneous compression/decompression for a combine full-duplex performance of 200 Mbytes/s clocking at 25 MHz. Both compression and decompression channels fit into a single A500K130 ProASIC FPGA with a typical compression ratio that halves the original uncompressed data. The device is specially targeted to enhance the performance of Gbit/s data networks and storage applications where it can double the performance of the original system.

A multi-cycle fixed point square root module for FPGAs

This paper presents a module that solves the square root by obtaining a number of more significant bits from a look-up table as an approximate root. A set of possible roots are then appended and squared for comparison to the original radicand, finely tuning the calculation. The module stops as soon as it finds an exact root, therefore not all entries take the same number of cycles, reducing the number of iterations required for full resolution. The proposed FPGA module overcomes a Xilinx’s logiCORE IP in terms of resources utilization and in several cases latency due to its flexible structure configuration.

FPGA-based architecture for computing testors

Irreducible testors (also named typical testors) are a useful tool for feature selection in supervised classification problems with mixed incomplete data. However, the complexity of computing all irreducible testors of a training matrix has an exponential growth with respect to the number of columns in the matrix. For this reason different approaches like heuristic algorithms, parallel and distributed processing, have been developed. In this paper, we present the design and implementation of a custom architecture for BT algorithm, which allows computing testors from a given input matrix. The architectural design is based on a parallel approach that is suitable for high populated input matrixes. The architecture has been designed to deal with parallel processing of all matrix rows, automatic candidate generation, and can be configured for any size of matrix. The architecture is able to evaluate whether a feature subset is a testor of the matrix and to calculate the next candidate to be evaluated, in a single clock cycle. The architecture has been implemented on a Field Programmable Gate Array (FPGA) device. Results show that it provides significant performance improvements over a previously reported hardware implementation. Implementation results are presented and discussed.

Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware

Data streams are unbounded and infinite flows of data arriving at high rates which cannot be stored for offline processing. Because of this, classical approaches for Data Mining cannot be used straightforwardly in data stream scenario. This paper introduces a single-pass hardware-based algorithm for frequent itemsets mining on data streams that uses the top-k frequent 1-itemsets. Experimental results of the hardware implementation of the proposed algorithm are also presented and discussed.