Claudio Favi

A 128

An imager for time-resolved optical sensing was fabricated in CMOS technology. The sensor comprises an array of 128times128 single-photon pixels, a bank of 32 time-to-digital-converters, and a 7.68 Gbps readout system. Thanks to the outstanding timing precision of single-photon avalanche diodes and the optimized measurement circuitry, a typical resolution of 97 ps was achieved within a range of 100 ns. To the best of our knowledge, this imager is the first fully integrated system for photon time-of-arrival evaluation. Applications include 3-D imaging, optical rangefinding, fast fluorescence lifetime imaging, imaging of extremely fast phenomena, and, more generally, imaging based on time-correlated single photon counting. When operated as an optical rangefinder, this design has enabled us to reconstruct 3-D scenes with milimetric precisions in extremely low signal exposure. A laser source was used to illuminate the scene up to 3.75 m with an average power of 1 mW, a field-of-view of 5deg and under 150 lux of constant background light. Accurate distance measurements were repeatedly achieved based on a short integration time of 50 ms even when signal photon count rates as low as a few hundred photons per second were available.

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Phase and intensity of light are detected simultaneously using a fully digital imaging technique: single-photon synchronous detection. This approach has been theoretically and experimentally investigated in this paper. We designed a fully integrated camera implementing the new technique that was fabricated in a 0.35 mum CMOS technology. The camera demonstrator features a modulated light source, so as to independently capture the time-of-flight of the photons reflected by a target, thereby reconstructing a depth map of the scene. The camera also enables image enhancement of 2D scenes when used in passive mode, where differential maps of the reflection patterns are the basis for advanced image processing algorithms. Extensive testing has shown the suitability of the technique and confirmed phase accuracy predictions. Experimental results showed that the proposed rangefinder method is effective. Distance measurement performance was characterized with a maximum nonlinearity error lower than 12 cm within a range of a few meters. In the same range, the maximum repeatability error was 3.8 cm.

128 Single-Photon Image Sensor With Column-Level 10-Bit Time-to-Digital Converter Array

This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed architecture, implemented in a 65nm FPGA system, consists of a pipelined interpolating time-to-digital converter (TDC). The TDC comprises a coarse time discriminator and a fine delay line, capable of sustained operation at a clock frequency of 300MHz. A Turbo version of the circuit implements a pipelined interpolating TDC with suppressed dead time to reach a conversion rate of 300MS/s at the expense of a systematic asymmetry that requires fast error correction. The TDCs proposed in this paper can be compensated for process, voltage, and temperature (PVT) variations using a conventional charge pump based feedback or a digital calibration technique. Results demonstrate the suitability of the approach for a variety of applications involving high-precision ultra-fast time discrimination, such as optical lifetime sensing, time-of-flight cameras, high throughput comlinks, RADARs, etc.

Single-Photon Synchronous Detection

We present an array of 128times128 highly miniaturized SPAD (single-photon avalanche diodes) pixels with a bank of 32 time-to-digital converters (TDCs) on chip. A decoder selects a 128-pixel row. Every group of 4 pixels in the row shares a TDC based on an event-driven mechanism. As a result, row-wise parallel acquisition is obtained with a low number of TDCs. Because of the outstanding timing precision of SPADs and an optimized TDC design, a typical resolution of 97 ps is achieved within a range of 100 ns (10 b) at a maximum rate of 10 MS/s per TDC. The TDC bank exhibits a DNL of 0.08LSB and an INL of 1.89LSB.

A 17ps time-to-digital converter implemented in 65nm FPGA technology

This work presents a multi-channel time-to-digital converter (TDC) based on a field-programmable gate array (FPGA). This TDC shares many advantages of custom circuitry but few of the drawbacks. A thorough characterization of the TDC, based on a Xilinx Virtex-6 FPGA, is presented and several performance parameters are described, including distortions due to the FPGA architecture, temperature effects, intra-chip position variation, and chip-to-chip variation. An optimized TDC exhibits 10ps resolution, 3.86LSB integral non-linearity, and a throughput of 300MS/s. Also, measurements are shown for TDC-to-TDC distortion for multi-channel TDCs and simulations are performed to investigate parallelism using multiple TDCs. Results imply that FPGA-based TDCs can achieve high performance, and can be used in a wide range of applications requiring high throughput and accurate time measurements.

A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution

A novel imaging technique is proposed for fully digital detection of phase and intensity of light. A fully integrated camera implementing the new technique was fabricated in a 0.35 mum CMOS technology. When coupled to a modulated light source, the camera can be used to accurately and rapidly reconstruct a 3D scene by evaluating the time-of-flight of the light reflected by a target. In passive mode, it allows building differential phase maps of reflection patterns for image enhancement purposes. Tests show the suitability of the technique and confirm phase accuracy predictions.

A multi-channel, 10ps resolution, FPGA-based TDC with 300MS/s throughput for open-source PET applications

In this paper we propose to replace all data and control pads generally present in conventional chips with a new type of ultra-compact, low-power optical interconnect implemented almost entirely in CMOS. The proposed scheme enables optical through-chip buses that could service hundreds of thinned stacked dies. High throughputs and communication density could be achieved even in tight power budgets. The core of the optical interconnect is a single-photon avalanche diode operating in pulse position modulation. We demonstrate how throughputs of several gigabits per second may be achieved. We also show a systematic analysis of the system and preliminary results to support its suitability in emerging DSM technologies.

Single-photon synchronous detection

We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical signal that is detected through a Single-Photon Avalanche Diode (SPAD) capable of timing uncertainties as low as 50 ps.The CIUs comprise a free-standing local oscillator serving a computing area of a few tens of square micrometers, thus resulting in extremely reduced power dissipations, since the distribution of a high frequency clock over long distances is avoided. This approach is based on the globally asynchronous locally synchronous con cept, whereby the granularity of the local domains is reduced to a minimum, thus enabling extremely high local clock frequencies and low power, while minimizing substrate noise injection and intra-chip interference. Thanks to this approach we can free ourselves from expensive synchronization techniques such as FIFOs, delays, or flip-flop based synchronizers by creating fixed synchronization points in time where data can be exchanged. The paradigm is demonstrated on a chip designed and fabricated in a standard 90 nm CMOS technology. A full characterization demonstrates the suitability of the approach.

Techniques for fully integrated intra-/inter-chip optical communication

Fabrication process introduces some inherent variability to the attributes of transistors (in particular length, widths, oxide thickness). As a result, every chip is physically unique. Physical uniqueness of microelectronics components can be used for multiple security applications. Physically Unclonable Functions (PUFs) are built to extract the physical uniqueness of microelectronics components and make it usable for secure applications. However, the microelectronics components used by PUFs designs suffer from external, environmental variations that impact the PUF behavior. Variations of temperature gradients during manufacturing can bias the PUF responses. Variations of temperature or thermal noise during PUF operation change the behavior of the circuit, and can introduce errors in PUF responses. Detailed knowledge of the behavior of PUFs operating over various environmental factors is needed to reliably extract and demonstrate uniqueness of the chips. In this work, we present a detailed and exhaustive analysis of the behavior of two PUF designs, a ring oscillator PUF and a timing path violation PUF. We have implemented both PUFs using FPGA fabricated by Xilinx, and analyzed their behavior while varying temperature and supply voltage. Our experiments quantify the robustness of each design, demonstrate their sensitivity to temperature and show the impact which supply voltage has on the uniqueness of the analyzed PUFs.