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semiconductor thermal measurement and management symposium | 2003

Thermal transient modeling and experimental validation in the European project PROFIT

Heinz Pape; Dirk Schweitzer; John H. J. Janssen; Arianna Morelli; Claudio Maria Villa

Results of the European project PROFIT on thermal transient measurement and modeling of IC packages are presented. All together 16 different packages from the three semiconductor manufacturers Infineon, Philips and ST Microelectronics were measured in four dual cold plate (DCP) environments as defined in the preceding DELPHI and SEED projects. Solutions to measure TO-type and fine pitch packages in the DCP, especially for the critical DCP-4 boundary condition were demonstrated, as well as reduction of interface resistance and increased reproducibility by using Woods alloy as an interface material. The measurements were simulated using the commercial software packages ANSYS/spl reg/, FLOTHERM/spl reg/ or MARC/spl reg/. The agreement between simulated and measured thermal impedance is quite good (<15%) from steady state (t=1000s) to transients with t<0.1s, i.e. 4 orders of magnitude. In a few cases, this level of accuracy was kept even over 7 orders of magnitude. Increasing relative inaccuracy with shorter transients corresponds to small absolute errors in temperature. So for practical pulse temperature prediction, the accuracy should already be sufficient, for extraction of geometrical and material parameters, it is probably not.A major objective of the European project PROFIT is to generate boundary condition independent (BCI) dynamic compact thermal models (DCTM) of semiconductor products. Extending the methods for steady BCI-CTM developed in preceding projects DELPHI and SEED to the transient domain, a detailed numerical model of the component is needed, which is validated against four dual cold plate (DCP) experiments extracting heat along the main heat flow paths from a package. The validated detailed model is then used for numerical experiments in many environments represented by external BC. Results are used to optimize resistors and capacitors of a small network forming the DCTM. This work is focused on the first part of developing validated detailed dynamic models by comparison of modeling and measurements. Results of the European project PROFIT on thermal transient measurement and modeling of integrated circuit packages are presented. All together sixteen different packages from the three Semiconductor Manufacturers Infineon, Philips, and ST Microelectronics were measured in four DCP environments as defined in the preceding DELPHI and SEED projects. Solutions to measure TO-type and fine pitch packages in the DCP, especially for the critical DCP-4 boundary condition were demonstrated, as well as reduction of interface resistance and increased reproducibility by using Woods alloy as an interface material. The measurements were simulated using the commercial software packages ANSYS, FLOTHERM, or MARC. The agreement between simulated and measured thermal impedance is 15% or better from steady state (t=1000 s) to transients with t>0.1, i.e., four orders of magnitude. In a few cases, this level of accuracy was kept even over seven orders of magnitude. Increasing relative inaccuracy with shorter transients corresponds to small absolute errors in temperature. So practical pulse temperature prediction will usually be correct within a few degrees. Extraction of geometrical and material parameters will need further improvement.


EuroSime 2006 - 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems | 2006

From Power SO to E-Pad packages: a thermal bargain?

Claudio Maria Villa; A. Morelli; D. Gualandris

Facing the demand of low cost solutions for medium power applications from various segments of the electronics market, a full thermal study comparing existing power SMD package families and new e-pad structures is performed. Different body sizes and pin counts are considered. The study consists of thermal modeling analysis carried on using FLOTHERMreg. Thermal simulation results with different PCB configurations are presented. The thermal dissipation mechanism for those packages through the metal bottom case to the PCB is described. The copper exposed area dimension soldered onto the PCB is identified as the dominating factor controlling the total package thermal resistance. Consequently the limits of applicability of new small body e-pad packages versus the old style power SMDs are finally defined


Archive | 1998

Card assembly of power device in plastic package with external heat sink soldered to the internal heat sink

Roberto Tiziani; Roberto Rossi; Claudio Maria Villa


Archive | 1997

Heat sink for surface mount power packages

Paolo Casati; Carlo Cognetti; Roberto Tiziani; Claudio Maria Villa


european microelectronics and packaging conference | 2009

Wafer level packaging fan out thermal management: Is smaller always hotter?

Donata Gualandris; Claudio Maria Villa


european microelectronics and packaging conference | 2013

Ball Grid Array package for automotive application: Strong link between design and 3D modeling

Giovanni Graziosi; Cristina Somma; Arianna Morelli; Claudio Maria Villa; Patrice Joubert Doriol; Laurent Marechal; Sebastien Gallois-Garreignot


Additional Conferences (Device Packaging, HiTEC, HiTEN, & CICMT) | 2010

A High Performance and Cost Effective Molded Array Package Substrate

Philip E. Rogren; Pierangelo Magni; Maura Mazzola; Mark Shaw; Giovanni Graziosi; Claudio Maria Villa


international conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems | 2018

BGA strip warpage induced by assembly process and the practical prediction methodology

Roseanne Duca; Jing En Luan; Phone Maw Hla; Claudio Maria Villa; Marco Rovitto


electronic components and technology conference | 2018

Dynamic Warpage Analysis of QFP Packages During Soldering Reflow Process and Thermal Cycle

Marco Rovitto; Arianna Morelli; Carlo Passagrilli; Claudio Maria Villa


Archive | 1997

Leiterplattenanordnung bestehend aus einem in einem Kunststoffgehäuse verpackten Leistungshalbleiterbauelement, dessen interne Wärmesenke mit einer externen Wärmesenke gelötet ist Printed circuit board assembly from a packaged in a plastic housing power semiconductor device whose internal heat sink is composed soldered to an external heat sink

Roberto Tiziani; Roberto Rossi; Claudio Maria Villa

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Marco Rovitto

Vienna University of Technology

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