Claus Dorschky

Compact InP-based HBT VCOs with a wide tuning range at W- and D-band

Compact monolithic integrated differential voltage-controlled oscillators (VCOs) operating in W-band were realized using InP-based heterojunction bipolar transistors (HBTs). The oscillators, with a total chip size of 0.6 by 0.35 mm/sup 2/, are based on a balanced Colpitts-type topology with a coplanar transmission-line resonator. By varying the voltage across the base-collector junction of the HBT in the current mirror and by changing the current in the VCO, the oscillation frequency can be tuned between 84 and 106 GHz. At 100 GHz, a differential voltage swing of 400 mV is obtained, which should be sufficient to drive 100 Gb/s digital logic. By combining the balanced outputs of a similar differential VCO in a push-push configuration, a compact source with close to -10 dBm output power and a tuning range between 138 and 150 GHz is obtained.

Measurement of the dispersion tolerance of optical duobinary with an MLSE-receiver at 10.7 Gb/s

We experimentally demonstrate a significant improvement in the dispersion tolerance of optical duobinary modulation when employing an MLSE instead of a standard receiver. We show that the improvement critically depends on the MLSE design.

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock data recovery (CDR) circuit is a key element for broad band optical communication systems at 40 Gb/s. We report a 40Gb/s CDR fabricated in Indium-Phosphide heterojunction bipolar transistor (InP HBT) technology using the more robust architecture of a phase lock loop with a digital early-late phase detector. The faster (compared to SiGe) InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This in turn reduces the circuit complexity (transistor count) and VCO requirements. The integrated IC includes an on-chip LC VCO and on-chip clock dividers to drive an external DEMUX and low frequency PLL control loop. On-chip limiting amplifier buffers are included for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed signal IC operating at the clock rate of 40 GHz. We describe the chip architecture and measurement results.

A fully-integrated 40 Gb/s clock and data recovery/1:4 DEMUX IC in SiGe technology

A 40 Gb/s clock and data recovery (CDR) IC with 1:4 demultiplexer (DEMUX) is fabricated in a SiGe technology. The architecture provides robust operation combined with a high level of integration, dissipating 4.8 W from a 5.5 V supply.

A 1:4 demultiplexer for 40 Gb/s fiber-optic applications

The demultiplexer (DEMUX) is a critical component of a fiber communication system. In order to satisfy increasing demands for data, fiber systems will employ several wavelengths carrying 40 Gb/s data in the near future. The requirements for such systems dictate that the DEMUX handle at least 4 channels of 10 Gb/s SONET/SDH data. The challenge is to build a 1:4 DEMUX that is both manufacturable and cost-effective to be integrated onto a receiver board. The authors describe a monolithic four-channel DEMUX for 40 Gb/s applications which uses an AlInAs/InGaAs HBT technology from a commercial foundry. Measurements demonstrate 40 Gb/s operation for 0.3 Vpp single-ended data input and 0.6 Vpp differential clock input.

A 40/43-Gb/s CDR/DEMUX and MUX chipset integrated on a MCM-ceramic with 3R-regeneration functionality

A second-generation 40/43-Gb/s CDR/DEMUX and MUX chipset in a 120-GHz-f/sub T/ SiGe technology is presented. While consuming 3.4-W, the fully-integrated CDR/DEMUX provides an electrical sensitivity of less than 40-mVpp at a BER of 10/sup -12/, the MUX consumes 2.3-W. Additionally, the integration of the chipset as a 3R-regenerator on a ceramic is demonstrated.