Coenrad J. Fourie

Three-dimensional multi-terminal superconductive integrated circuit inductance extraction

Accurate inductance calculations are critical for the design of both digital and analogue superconductive integrated circuits, and three-dimensional calculations are gaining importance with the advent of inductive biasing, inductive coupling and sky plane shielding for RSFQ cells. InductEx, an extraction programme based on the three-dimensional calculation software FastHenry, was proposed earlier. InductEx uses segmentation techniques designed to accurately model the geometries of superconductive integrated circuit structures. Inductance extraction for complex multi-terminal three-dimensional structures from current distributions calculated by FastHenry is discussed. Results for both a reflection plane modelling an infinite ground plane and a finite segmented ground plane that allows inductive elements to extend over holes in the ground plane are shown. Several SQUIDs were designed for and fabricated with IPHTs 1 kA cm − 2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures that span different layers, include vias, inductively coupled control lines and ground plane holes. We measured the loop inductance of these SQUIDs and show how the results are used to calibrate the layer parameters in InductEx and verify the extraction accuracy. We also show that, with proper modelling, FastHenry can be fast enough to be used for the extraction of typical RSFQ cell inductances.

Status of Superconductor Electronic Circuit Design Software

More than a decade has elapsed since the publication of the last thorough evaluation of the global state of superconductor electronic (SCE) design software, and seven years since the publication of the 2005 SCENET roadmap. In this work we discuss the progress made to date on SCE design software, present a critical analysis of the capabilities of the software available today, and attempt to lay the foundation of a roadmap for SCE design software to complement published hardware and technology roadmaps. The discussion includes design techniques, circuit optimizers, logic simulators, inductance calculators, simulation engines, full-wave EM solvers and the NioCAD project. We also discuss requirements not yet met.

Comparison of genetic algorithms to other optimization techniques for raising circuit yield in superconducting digital circuits

Novel logic devices in the RSFQ and COSL superconducting logic families are most often sub-optimal. Before such devices can be incorporated into physical designs, they have to be optimized for high theoretical yield, and preferably for highest possible yield. Even simple logic gates can contain numerous inductors, resistors and Josephson junctions. During optimization, it is often needed to adjust all the element values. The search space is therefore very large, and genetic algorithms have been used with success to optimize such gates. The conversion of circuit file to genome for the genetic algorithms is discussed, as well as fitness evaluation through Monte Carlo analysis. Results with both novel and existing logic gates are presented. Other optimization techniques are also discussed in comparison to genetic algorithms.

Simulated inductance variations in RSFQ circuit structures

Manufacturing tolerances influence circuit parameters, and inductance is no exception. A computer application was developed to fully automate inductance calculation as part of a layout extraction suite. InductEx takes a GDSII layout file as input, finds the inductance ports, extracts structures, applies mask-to-wafer offsets and random process tolerances to the circuit structures, builds deck files that can be processed with FastHenry, and manages FastHenry-all autonomously. Results are presented for the simulated variation in inductance-both self and mutual, over hundreds of runs-in several common RSFQ structures in the Hypres 1 kA/cm/sup 2/ process (with the latest tolerance values built in), even with the presence of moats.

Complete Monte Carlo model description of lumped-element RSFQ logic circuits

Over the last decade, Monte Carlo simulations have emerged as the most useful way of predicting the yield of RSFQ circuits, as they consider all manufacturing tolerance effects on a circuit, and are not restricted to bias current variations. Here we finally present a comprehensive definition of layout-extracted Monte Carlo model creation for lumped-element Spice simulations-from the local and global values for inductance, resistance and junction area from statistical models, to the inclusion of parasitics, layer-to-layer variations, variations in the penetration depth, and capacitance and mutual coupling. Finally, the addition of bias current trimming to the simulations to compensate for most global variations is described, and comparative yield results listed.

Calibration of Inductance Calculations to Measurement Data for Superconductive Integrated Circuit Processes

It is easy to adjust the parameters for field-solver inductance extraction models to fit a single measurement. However, more effort is required to calibrate a model for a representative collection of line widths, layers, and fabrication runs. Numerically calculated inductance is also a strong function of segment size. A segment size is selected to optimize extraction accuracy versus speed for large RSFQ logic cells. InductEx is then calibrated for this segment size. Measured data from 54 test structures of different widths and layers, repeated on many chips over 22 wafers of Hypress 4.5 kA/cm2 mask aligner process and 48 test structures from 5 wafers for the wafer stepper process, were used to find the Hypres process averages. Artificial changes to InductEx layer parameters such as mask-wafer bias and penetration depth are used to first reduce skew between results for different widths, and then differences between layers. This results in a set of calibrated process parameters for inductance calculations with InductEx for both the mask aligner and wafer stepper processes from Hypres. Calibrated inductance calculation results agree with the average measurements with a root-mean-square error smaller than 2.3% over the full range of line widths from 0.8 μm to 20 μm, showing InductEx as a useful tool for narrow-line inductance calculations.

YBCO Josephson Junctions and Striplines for RSFQ Circuits Made by Ion Irradiation

We have investigated the electrodynamic properties of high-Tc Josephson junctions (JJs) and striplines made by ion irradiation in order to evaluate the potential of such a technology for low-power rapid single flux quantum superconductor digital electronics. The process is briefly presented, together with the JJ characteristics in the context of high-speed electronics. Line inductances of different geometries and at different temperatures have been measured through superconducting quantum interference device (SQUID) modulation. A detailed comparison with 3-D numerical calculations has been made, and a quantitative agreement that shows typical values of 4-8 pH per square without a ground plane, depending on linewidth and the gap to the ground line, has been obtained.

An RSFQ DC-resettable latch for building memory and reprogrammable circuits

A new RSFQ latch, the DC-Resettable Latch (DCRL), is introduced. The DCRL functions like a standard nondestructive readout register (NDRO), except that it requires a dc current or current pulse to reset. This allows the DCRL to be used as a memory element in large memory blocks, where the entire block can be erased with a current pulse from a single threaded current line instead of unwieldy pulse distribution circuitry. The reset current can be applied by off-chip control logic, or on-chip bipolar current elements such as HUFFLEs. However, the DCRL is most useful as the base building block of complex reprogrammable RSFQ circuitry.

Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx

At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.

Experimental Investigation of Energy-Efficient Digital Circuits Based on eSFQ Logic

We present the design and results of experimental verification methods for ultra-low-power digital circuits based on the recently introduced energy-efficient single flux quantum (eSFQ) logic. Similar to another low-power SFQ logic, ERSFQ, eSFQ circuits make use of superconducting dc bias current dividers and thus avoid static power dissipation. As a result, per-gate power dissipation is reduced by two orders of magnitude as compared to conventional rapid single flux quantum and static power dissipation is zero. The eSFQ circuits are fabricated using the HYPRES standard 4.5 kA/cm2 process. We integrate a low-pass analog-to-digital modulator with our eSFQ deserializer to enable testing at high speed. In this paper, we demonstrate the viability and performance metrics of eSFQ circuits through functional and high-speed tests. Specifically, we confirmed correct operation and present measured parameter margins.