W.J. Perold

Monte Carlo optimization of superconducting complementary output switching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.

Complementary output switching logic-a new superconducting voltage-state logic family

A new superconducting logic family, complementary output switching logic (COSL), is proposed. The family consists of AND, NAND, OR, NOR, and XOR gates. The performance of the gates is predicted with a procedure that evaluates the dynamic performance when all circuit parameters are randomly varied around the nominal values. The simulated performance of the gates is compared with modified variable threshold logic (MVTL) at 5 GHz and 10 GHz. The functionality and margins of the COSL gates are verified by measurements at low speed.

SUPERCONDUCTING COMPLEMENTARY OUTPUT SWITCHING LOGIC OPERATING AT 5-10 GB/S

We present experimental results of superconducting voltage‐state complementary output switching logic gates operating 10 Gb/s and 2‐bit encoder circuits clocked at 5–8 Gb/s. The logic gates and circuits were designed using a Monte Carlo optimization process so that they have a high theoretical yield at 5–10 Gb/s in spite of existing Josephson junction process variations.

Comparison of genetic algorithms to other optimization techniques for raising circuit yield in superconducting digital circuits

Novel logic devices in the RSFQ and COSL superconducting logic families are most often sub-optimal. Before such devices can be incorporated into physical designs, they have to be optimized for high theoretical yield, and preferably for highest possible yield. Even simple logic gates can contain numerous inductors, resistors and Josephson junctions. During optimization, it is often needed to adjust all the element values. The search space is therefore very large, and genetic algorithms have been used with success to optimize such gates. The conversion of circuit file to genome for the genetic algorithms is discussed, as well as fitness evaluation through Monte Carlo analysis. Results with both novel and existing logic gates are presented. Other optimization techniques are also discussed in comparison to genetic algorithms.

Simulated inductance variations in RSFQ circuit structures

Manufacturing tolerances influence circuit parameters, and inductance is no exception. A computer application was developed to fully automate inductance calculation as part of a layout extraction suite. InductEx takes a GDSII layout file as input, finds the inductance ports, extracts structures, applies mask-to-wafer offsets and random process tolerances to the circuit structures, builds deck files that can be processed with FastHenry, and manages FastHenry-all autonomously. Results are presented for the simulated variation in inductance-both self and mutual, over hundreds of runs-in several common RSFQ structures in the Hypres 1 kA/cm/sup 2/ process (with the latest tolerance values built in), even with the presence of moats.

Complete Monte Carlo model description of lumped-element RSFQ logic circuits

Over the last decade, Monte Carlo simulations have emerged as the most useful way of predicting the yield of RSFQ circuits, as they consider all manufacturing tolerance effects on a circuit, and are not restricted to bias current variations. Here we finally present a comprehensive definition of layout-extracted Monte Carlo model creation for lumped-element Spice simulations-from the local and global values for inductance, resistance and junction area from statistical models, to the inclusion of parasitics, layer-to-layer variations, variations in the penetration depth, and capacitance and mutual coupling. Finally, the addition of bias current trimming to the simulations to compensate for most global variations is described, and comparative yield results listed.

A novel method to measure the generated voltage of a ZnO nanogenerator

A novel method to measure the output voltage of a zinc oxide nanowire nanogenerator is proposed. Various tests are performed to verify that the output voltage does indeed originate from the nanogenerator and not from environmental noise. Although noise does influence the output voltage measurements, the output voltage is easily distinguishable from the measured noise. It is also shown that the method can be used to determine the internal resistance of the nanogenerator by measuring the output voltage over different output resistors.

Fabrication of submicron YBCO Josephson junctions by a sample mosaic navigation assisted laser etching process

Taking advantage of a New Wave 213 nm laser system, equipped with high-precision submicron resolution sample mosaic navigation, we are able to laser-etch and fabricate planar submicron-size Josephson junctions on YBa2Cu3O7−x thin films successfully. The entire process of laser etching and sample navigation is software controlled. The widths were measured by atomic force microscopy (AFM), and they range from 0.7 to 1.4 µm. We report on the observed I–V characteristics and Shapiro steps, which confirm the Josephson effect in these junctions. The measured critical current dependence on temperature shows a linear relationship for micron-size constrictions. In the case of submicron constrictions, the dependence is an exponential decay type, consistent with diffusive long S–N–S junction behaviour. It is believed that the observed behaviour can be ascribed to laser heating of the constriction material, changing the superconducting phase to the normal one.

An RSFQ DC-resettable latch for building memory and reprogrammable circuits

A new RSFQ latch, the DC-Resettable Latch (DCRL), is introduced. The DCRL functions like a standard nondestructive readout register (NDRO), except that it requires a dc current or current pulse to reset. This allows the DCRL to be used as a memory element in large memory blocks, where the entire block can be erased with a current pulse from a single threaded current line instead of unwieldy pulse distribution circuitry. The reset current can be applied by off-chip control logic, or on-chip bipolar current elements such as HUFFLEs. However, the DCRL is most useful as the base building block of complex reprogrammable RSFQ circuitry.

Experimental demonstration of complementary output switching logic approaching 10 Gb/s clock frequencies

We have proposed a new type of voltage-state logic called Complementary Output Switching Logic (COSL). The COSL circuits were optimized for 5-10 GHz operation using a Monte Carlo method. Here we present experimental test results of the basic COSL gates in the frequency range 1-10 GHz, and discuss bit error rate measurements at 2-5 Gb/s.