Colin McDonough

Demonstration of an Optical Chip-to-Chip Link in a 3D Integrated Electronic-Photonic Platform

A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26μA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy.

TSV Stress Testing and Modeling for 3D IC Applications

The stress investigation on through-silicon vias (TSVs) is important for 3D IC development. This work summarizes the stress measurement and modeling results for TSVs based on the use of micro-Raman Spectroscopy, which can be used to determine the material, process and design of TSVs. More importantly, this study can provide an important guideline for the reliability analysis of the TSV-based 3D IC.

Thermal and spatial profiling of TSV-induced stress in 3DICs

The thermal and spatial variation of Cu through silicon via (TSV)-induced stress in 300mm Si wafers has been investigated for both isolated TSVs and TSV arrays using top-down and cross-sectional spectral microRaman imaging. The TSV-induced stress in Si results from plastic yield of the Cu, is compressive in the immediate vicinity of the TSV, and transitions to a tensile state at larger separations - in quantitative agreement with finite element modeling (FEM). TSV arrays (linear and square) lead to substantial tensile stress enhancement within the array. Moreover, thermal annealing showed that the intra-array Si stress field became more compressive with increased post-CMP thermal annealing while the Si stress-field external to the arrays exhibited little change. This may open potential avenues for reduction of TSV-induced Si stress in 3DICs.

Thermal and spatial dependence of TSV-induced stress in Si

The thermal and spatial variation of Cu TSV-induced stress has been investigated for 1×4 arrays of 5 µm diameter × 50 µm TSVs using microRaman imaging. Following post-CMP annealing the measured Si Raman shift outside the TSV array is slightly modified. In strong contrast, the Si Raman shift midway between TSVs transitions from a tensile to compressive state as the annealing temperature increases. Topographic analysis implies this shift is associated with thermally-induced Cu extrusion.

High-density 3D electronic-photonic integration

Todays electronic photonic integration approaches involve various trade-offs between integration complexity, cost and performance, with no single approach being able to satisfy both the high-performance and low cost/complexity requirements. Luxteras process [1] represents monolithic integration, which has low parasitics and customized photonics but slow transistors. Oracles [2] and ST Micro [3] integrate photonic chips and electronic chips through face-to-face micro-bump/copper-pillar bonding, which enables fast transistors, optimized photonics but at the cost of high interconnection parasitics (both electrical wirebond to the outside world and chip-to-chip bumps) which limit the link performance. Another monolithic approach recently demonstrated monolithic integration of photonic components in an advanced process node (45nm SOI) [4] and offers the promise of high-speed transistors, low-parasitics, but somewhat constrained photonic devices. In this paper, we illustrate an alternative approach that we recently demonstrated, which aims to offer the best of both worlds by performing 3D integration of electronic and photonic wafers with very low interconnection parasitics. In Figure 1, we illustrate the process in which the photonic SOI wafer is oxide bonded face-to-face with the CMOS wafer (shown on the bottom). The substrate of the photonic wafer is then removed and connections between the CMOS wafer and the photonic wafer are established through tight-pitch shallow (depth less than 7um) through-oxide vias (TOVs). The parasitic capacitance of the TOV is estimated to be around 3fF from on-chip de-embedding structures. This is critical to improved energy efficiency of the transmitter and receiver sensitivity to optical power. In comparison, the capacitance of the micro-bump/copper-pillar connection is at least 10x larger. Figure 2 illustrates one of the chip templates in this electronic-photonic development platform. This chip template hosts 16 complete photonic transceiver modules, each implemented to enable up to 8 different modulators and photo-detectors to be tested with the same electronic back-end, to aid in process characterization and device development. Each front-end in this multi-cell macro consists of the modulator driver with serializer and thermal-tuning lock circuitry, a receiver with deserializer and thermal lock circuitry and a common digital back-end for data-generation, link performance monitoring and configuration. This development platform template yields 1000s of functional photonic components as well as 16M transistors per chip module. Figure 3 illustrates a full optical chip-to-chip link is demonstration. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26μA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy.

Investigation of Apertureless NSOM for Measurement of Stress in Strained Silicon‐on‐Insulator Test Structures

Strain in blanket and patterned silicon‐on‐insulator (SOI) structures have been investigated via apertureless near‐field scanning Raman spectroscopy to investigate the efficacy of so‐called tip‐enhanced Raman scattering (TERS) for Si strain characterization and metrology for integrated circuit (IC) devices. The current study considers TERS generation using tapered capillary tips terminated with a metallized particle in a normal‐incident‐beam geometry. TERS enhancement exceeding 20% has been observed in blanket and patterned SOI structures wherein the device layer has been fabricated with an engineered strain of 0.075%. Patterns consisting of arrays of isolated device‐layer ‘mesa’ structures (2 μm diameter) were investigated in a differential mode wherein the far‐field signal was subtracted from the TERS signal during spatial profiling of both strained (device‐layer) and unstrained (bulk) Si Raman peaks. A stable differential signal was observed and corresponded uniquely to the strained device layer. This ...