Cong-Kha Pham

A Low-Power High-PSRR Low-Dropout Regulator With Bulk-Gate Controlled Circuit

In this brief, we presented a bulk-gate controlled circuit for improving a power supply rejection ratio (PSRR) of a low-dropout voltage regulator (LDO), which deteriorated due to lowering of a power consumption. A test chip was fabricated using a 0.18-¿m complimentary metal-oxide-semiconductor process, and experimental results demonstrated that the proposed circuit provides the PSRR that improved to 77 dB at 10 Hz and 64.3 dB at 1 kHz, while the consumption current of the whole LDO with all component circuits was 8.5 ¿A without a load and 35 ¿A with a full load.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.

CMOS Schmitt Trigger Circuit with Controllable Hysteresis Using Logical Threshold Voltage Control Circuit

A simple logical threshold voltage control circuit is proposed. It can be implemented using normal conventional CMOS inverters. The proposed circuit is able to control a logical threshold voltage of a gate linearly and continuously over a range of a power supply voltage. Applications to the Schmitt trigger circuit with controllable hysteresis and a window comparator are shown to demonstrate practical usages of the proposed circuit.

A DC-DC Converter using a high speed soft-start control circuit

In this paper, a high speed soft-start control circuit is proposed to implement the Current-Mode DC-DC Converter. The time for the soft-start does not depend on the load condition from no load to the maximum load current. The proposed circuit consists of SSRAMP, VREFRAMP and a small differential-voltage generator. The SSRAMP is a piecewise linear voltage that has four different ramps. The VREFRAMP is a linear ramp voltage. The HSPICE simulation results show that the proposed high speed soft-start control circuit to implement to the Current-Mode DC-DC Converter achieved 150μs and has been shortened to 1/50 compared with a commonly available high performance converter which achieves in about 7.5ms.

A compact adaptive slope compensation circuit for Current-Mode DC-DC converter

In this paper, the adaptive slope compensation circuit operating in low power consumption with a less component counts design is proposed. The sub-harmonic oscillation is a well-known problem in the Current-Mode DC-DC converters. Proposed novel adaptive slope compensation circuit solved the sub-harmonic oscillation problem. The circuit adjusts the slope compensation ramp by automatic operation according to the output voltage. The proposed circuit has implemented to the Current-Mode DC-DC converter which operates at 1.2MHz of the switching frequency. The proposed circuit used standard 0.5/im CMOS parameters for HSPICE simulation. The proposed circuit which composed of 15 components and consumes only 10/iA has eliminated the sub-harmonic oscillation problem.

An efficient FPGA-based database processor for fast database analytics

Recent years have witnessed a massive growth of global data due to the ubiquitous internet-of-thing products, social networking services, and mobile devices. Fast database analytics, therefore, has been increasingly attractive to numerous research. In this paper, a low-latency FPGA-based Database Processor (DBP) using bitmap index is proposed. By exploiting available embedded memory blocks and logic elements, a 50-MHz DBP is capable of performing 1,024 queries for entire 32,768 4-KB records within around 3.31 ms. In other words, the DBP can analyze a capacity data of nearly 37.76 GB per second.

New design method of low power over current protection circuit for low dropout regulator

In this paper, a low power current protection circuit implemented in LDOs is presented. The proposed circuit, designed in 0.35µm CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed the proposed circuit is operable in the regulator output voltage range V OUT = 1.2V to V OUT = 3.6V and supply voltage range V DD = V OUT + 0.5V to V DD = 5.6V . Since the proposed circuit is composed of few simple basic circuits such as comparator, Schmitt Trigger, it has a low current consumption which is less than ISS = 0.82µA at load current ILOAD = 200mA. This makes the circuit suitable for low power and low voltage LDO design.

Quick response circuit for low-power LDO voltage regulators to improve load transient response

In this work, we propose a quick response circuit to improve the load transient response of fully low dropout voltage linear regulator (LDO) which is operable with a very low power consumption. Simulating by HSPICE with 0.35 mum CMOS technology shows that we can achieve the transient responses with less transient overshoot or undershoot when driving large current loads. Comparing to the generic LDO, for example, in case of 1 muF decoupling capacitor, about 95% output drop and 27% settling time for 0.1 mA to 100 mA load current and 88% output overshoot and 63% settling time for 100 mA to 0.1 mA load current have been together improved. The proposed circuit only dissipates low static power, so we could achieve the above LDO with only 3.3 muA consuming current at V out + 1 V and 150 mA load current. V out is the output voltage of the regulator.

A wide frequency range and adjustable duty cycle CMOS ring voltage controlled oscillator

This paper presents a voltage controlled ring oscillator (VCO) with wide tuning range and adjustable duty cycle. The circuit was designed using Rohm 0.18µm technology with 1.5V supply voltage. The simulation results show that the VCO oscillates from 300Hz up to 1.4GHz, while the duty cycle can be adjusted 20–80% independently from the oscillating frequency.

Improvement of LDO's PSRR deteriorated by reducing power consumption : Implementation and experimental results

In this work, a Bulk-Gate Controlled Circuit, for improving power supply rejection ratio (PSRR) of a Low Dropout Voltage Regulator (LDO) which deteriorates due to lowering of power consumption is proposed. A test chip was fabricated using 0.18-µm CMOS process. Experimental results of the test chip demonstrate that the proposed circuit provides a high performance of PSRR which is up to 77 dB at 10 Hz, and 64.3 dB at 1 KHz, while the consumption current of the whole LDO which includes currents of all component circuits such as a reference circuit, an over current protection circuit, ect., is reduced to 8.5µA without load, and 35µA with full load. Comparing to the basic type of conventional LDOs, PSRR of the proposed Bulk-Gate Controlled LDO achieves an improvement of 16 dB for 10 Hz and 27.8 dB for 1 KHz .