Hong-Thu Nguyen

An efficient FPGA-based database processor for fast database analytics

Recent years have witnessed a massive growth of global data due to the ubiquitous internet-of-thing products, social networking services, and mobile devices. Fast database analytics, therefore, has been increasingly attractive to numerous research. In this paper, a low-latency FPGA-based Database Processor (DBP) using bitmap index is proposed. By exploiting available embedded memory blocks and logic elements, a 50-MHz DBP is capable of performing 1,024 queries for entire 32,768 4-KB records within around 3.31 ms. In other words, the DBP can analyze a capacity data of nearly 37.76 GB per second.

Low-Resource Low-Latency Hybrid Adaptive CORDIC With Floating-Point Precision

Despite being proposed since more than 50 years ago, COordinate Rotation DIgital Computer (CORDIC) is still one of the most effective algorithms for elementary function calculation so far. Original CORDIC, however, suffers high latency due to its nature of unvarying number of rotations. As a result, a low-latency hybrid adaptive (HA) CORDIC is proposed in this paper. Firstly, adaptive angle selection decreases total iterations up to 50% with respect to higher accuracy of results. Secondly, hybrid architecture including fixed-point input and floating-point output reduces the total hardware utilization and enhances the dynamic range of final results. Lastly, parallel and pipeline processing together with resource sharing technique allow the design to operate fully at 175.7 MHz with low resource consumption 1,139 LUTs and 489 registers.

An FPGA approach for high-performance multi-match priority encoder

In this paper, a scalable high-performance multi-match priority encoder (MPE) for information retrieval is presented. This approach deploys a new design architecture to construct the large-sized MPEs by using an 8-bit priority encoder as a basement. The experiments in an 8-bit MPE, 64-bit MPE, and 2,048-bit MPE prove that the achieved throughputs are 1.5 times, 1.7 times, and 1.4 times as high as those of previous works. Furthermore, a 4,096-bit MPE is fully operational in an information retrieval system and is capable of returning one match per clock cycle. At the operating frequency of 75MHz, the processing time in worst and best case are 54.6 μs and 0.03 μs, respectively.

SAR: A Self-Adaptive and Reliable protocol for wireless multimedia sensor networks

Recent years have witnessed a substantial growth in wireless multimedia sensor networks (WMSNs) due to the development of low-cost camera together with low-power system-on-chip (SoC). Unlike previous wireless sensor networks (WSNs), WMSNs strictly requires sustained multimedia data to be delivered over long periods of time, in contrast to the environmental noises. In this paper, Self-Adaptive and Reliable Point-to-Point (SAR) protocol for WMSN is presented. This transport protocol not only guarantees to dispatch all messages successfully but also adapts the data rate of the higher layer to prevent the network from congestion. The design is validated in a pair of Raspberry Pi and Atmel AT86RF212 module under different conditions. The experimental results indicate that SAR can carry out a wide range of transmission rates, from 16.6 to 470.5 Kbps, with distance up to 50 m. Moreover, the number of lost messages is eliminated around 47%, upon the utilization of proposed self-adaptive framework, Decrease Quickly Increase Slowly (DQIS).

A parallel pipeline CORDIC based on adaptive angle selection

Coordinate Rotation Digital Computer (CORDIC) was an efficient algorithm to compute elementary arithmetic such as multiplication, division, and root extractions. However, conventional CORDIC algorithm requires high latency to obtain the results. This paper proposes a low latency parallel pipeline CORDIC (PP-CORDIC) to calculate trigonometric functions. The results show that PP-CORDIC can operate at 83.64 MHz frequency with the latency was 10, 15, and 17 clock cycles in the best, average, and worst case, respectively. The hardware architecture occupies 7,035 LUTs, and 3,409 registers on Stratix IV FPGA.

Parallel pipelining configurable multi-port memory controller for multimedia applications

Despite many significant improvements of processors up to now, the off-chip memory performance has still lagged far behind. The high-performance memory controller, therefore, has become the key to success. In this paper, a parallel pipelining configurable multi-port memory controller is proposed to not only exploit the external memory bandwidth effectively, but also provide the flexibility in use and the independence from other system architectures. The proposed architecture is composed of multi-clock multi-data-width buffers to speed up the transactions, embedded memory to store the configuration, and priority scheme arbiter to schedule all access. The design, then, is evaluated in a low-cost low-power Altera Cyclone V FPGA with 1 GB DDR3 external memory. The experimental results demonstrate that the proposed controller can support up to 32 concurrent connections with various clocks and data width, and achieve approximately 82% and 87% of theory peak bandwidth in write and read process, respectively.

A CORDIC-based QR decomposition for MIMO signal detector

The purpose of this article is to propose a CORDIC-based QR Decomposition (CQRD) for MIMO Signal Detector module with qualities of low-resource and low-latency. The design contains four stages with six CORDIC modules in which its hardware architecture employs both vectoring and rotation mode equations. The evaluated results of CORDIC-based QRD prove that the proposed hardware design is high performance, low resource, and low latency. Because of the advantages of CQRD, it is suitable for the signal detector in MIMO systems.

A Low-Power Hybrid Adaptive CORDIC

The purpose of this brief is to introduce a hybrid adaptive coordinate rotation digital computer (HA-CORDIC) implemented on 65-nm silicon on thin buried oxide technology. The supply voltage of HA-CORDIC ranges from 0.25 V to 1.2 V and the lowest energy in active mode and sleep mode are 2.4 pJ/cycle and 0.003 pJ/cycle, respectively. By changing body bias voltages, the leakage current can be reduced to as small as 1.0 nA. Its experimental results proves that HA-CORDIC is potentially a good choice for low-power and high-precision applications in comparison with the previous work.

Highly parallel bitmap-based regular expression matching for text analytics

Text analytics has become increasingly important in the past few years because of the substantial growth in the amount of research, business, and government needs. An efficient text analytics system is likely to require high-powered regular expression matching (REGEX), as REGEX operations dominate the whole execution time. Some approaches have exploited the parallelism of graphic processing units (GPUs) and field-programmable logic arrays (FPGAs) to boost REGEXs performance. Nevertheless, those approaches still used finite-state automaton to detect the given patterns while automation structure is naturally inadequate for parallel processing. In this paper, we propose a completely different hardware architecture of REGEX that employs a bitmap index instead of the finite-state automaton. Internal logic gates/registers and embedded memory of FPGA are used to construct the query processing units and a bitmap index, respectively. The experimental results on an Intel Arria V FPGA prove that our REGEX is fully operational at 100 MHz and can process a 64-character query inside a 64-KB text data within 43.76 μs. The throughput achieved, therefore, reaches 11.98 Gbps.

FPGA-based frequent items counting using matrix of equality comparators

In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the Altera Arria V SoC Development Kit. The experimental results show that the implementation can perform on the maximum clock frequency of 40.85 MHz and requires 51,094 ALUTs and 8,417 registers, which is about 29% of the FPGAs resources. The average throughput performance achieves 1,280 millions items per second, which is about 50 times faster than that of the software-based application at the same setting.