Constantine A. Neugebauer

Comparison of Wafer Scale Integration with VLSI Packaging Approaches

A comparison is made of various high-density packaging approaches, including printed wiring board, thick-film hybrids, and wafer scale integration (WSI). Criteria include power dissipation, density, delays, and cost. It is concluded that thin-film hybrids using state-of-the-art VLSI chips have the potential for WSI density and performance. The requirement for fault tolerance, additional levels of metallization, excess power dissipation, process conservatism to achieve finite yield, and the nonoptimum nature of the Al/Si0 2 transmission line for cross wafer communication have made WSI noncompetitive.

Endurance and memory decay of MNOS devices

The endurance of MNOS EAROM‐type memory devices toward write/erase cycling is examined using the increase of the memory window decay rate as the criterion. Two decay regimes are identified: a short‐term decay in which the window decays linearly with log time, and a long‐term decay in which the rate is faster than log time. Beyond 104 write/erase cycles the short‐term decay rate increases at a rate of 0.05 V per decade of decay per decade of write/erase cycling per volt of memory window being cycled, at room temperature. Cycling also results in a deeper stored charge centroid in the nitride. Increasing the temperature during writing increases the depth of the stored charge in the nitride at a rate of 1.6±0.3 A/°C and decreases the short‐term decay rate. The degree of temperature dependence of the short‐term decay rate is a function of the write temperature and the number of accumulated write/erase cycles. The storage time tB at which the long‐term decay commences is found to shift toward shorter times on c...

Solder Fatigue Problems in Power Packages

The fatigue of solder connections in power packaging has been investigated. Power devices use large bond areas which lead to fatigue life problems. Three different types of structures consisting of silicon diodes attached to copper heatsinks have been thermally cycled and the integrity of the bonds compared. The thermal resistance from the silicon diode to its heatsink has been used to measure bond quality. Use of n BeO strain buffer between the silicon chip and the copper heatsink (Type II) improved the solder cycle life. Further addition of a layer of structured copper between the BeO and the copper sink (Type III resulted in marked additional improvement in cycle life. Fatigue failure was indicated by a rapid rise in the thermal resistance that suggested a crack or tear in one of the bonds between the silicon and the heat sink. This model has been confirmed by an ultrasonic microscope scan. Solder fatigue life was also extended by the use of hard solders, compressive forces, and hermeticity.

Hot Spots Caused by Voids and Cracks in the Chip Mountdown Medium in Power Semiconductor Packaging

The temperature increase under power dissipation in large semiconductor Chips mounted down with solder containing voids or cracks is explained in terms of two void types. They are distinguished on the basis of transient and steady-state thermal resistance measurements, and differ from each other in that for one the increased thermal resistance is mitigated by a reduced current density, but not for the other. They have been verified experimentally, and explain a large range of thermal and electrical characteristics, Such as occur in fatigue cycling.

Eliminating threshold losses in MOS circuits by bootstrapping using varactor coupling

Threshold losses reduce speed and increase power consumption of MOS digital circuits. A method to eliminate these losses is described. This is accomplished by the application of bootstrapping, in which a temporarily isolated circuit node is capacitatively coupled to the input voltage. The advantages of a MOS varactor element and its use for the coupling capacitor are described.

A 36-chip multiprocessor multichip module made with the General Electric high density interconnect technology

A unique packaging and interconnect technology was used to build a multichip, four-CPU-element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed circuit board methods. Reduced interconnect capacitance coupled with elimination of conventional package parasitics allowed clocking of commercial 40 MHz parts to nearly 90 MHz.<<ETX>>

I‐V characteristics of MOS capacitors with polycrystalline silicon field plates

The I‐V characteristics of MOS capacitors utilizing polycrystalline p‐type silicon field plates were investigated. It was found that sizable current flow is observable in both directions under pulsed dc conditions at voltages much below those at which current flows under applied dc. This suggests that the polycrystalline silicon film can be driven into avalanche and thus inject electrons into the oxide as well as the single‐crystal Si wafer. Charge trapping during passage of avalanche injected currents was observed to occur principally at the silicon/oxide interfaces. The rate of trapping depended strongly on the boron content of the oxide.

Channel Shortening in MOS Transistors during Junction Walk‐Out

The walk‐out of the breakdown voltage of the junctions of p‐channel MOS transistors was found to be accompanied by an increase in the transconductance. An explanation for this relationship is offered here in terms of electron injection into the gate oxide near the junctions, and subsequent trapping there. The rate of junction walk‐out depends not only on the total injected negative charge, but also on the value of the injection current itself, increasing at higher injection currents. The ratio of the injection current to the total junction current is found to decrease with increasing breakdown voltage.

The single chip versus multichip packaging option for digital CMOS in the 1990s

The level of functional density achievable in digital CMOS logic chips is so high that in the past systems implementations by multichip module (MCM) packaging appear to have been unnecessary, because the system was usually made up of only a few chips. However, rapidly increasing system sizes anticipated in the future will require many VLSI/ULSI CMOS chips per system, operating at near 100 MHz clock frequency. The authors have, therefore, reexamined the single-chip versus MCM packaging option for digital CMOS for the 1990s. They conclude that, for large-scale CMOS logic systems constructed by the use of many state-of-the-art VLSI/ULSI chips, the MCM packaging approach gives a manyfold improvement in packing density (3-8*), performance (up to 1.4*), and cost (1.2*) over the SCM packaging approach. >

Electrically erasable buried-gate nonvolatile read-only memory

An electrically erasable buried (floating) gate memory is described. The memory is programmed by electron injection by junction avalanche. An internal voltage multiplication scheme using varactor bootstrapping is used which makes nearly 40 V available at the memory cell for programming, yet requires input voltages no higher than 25 V. Erasure takes place by modified Poole-Frenkel conduction in a Si3N4film of 700-Å thickness which overlays the buried gate. Standard silicon gate p-MOS processing is used with only minor modifications. Memory retention is excellent and is extrapolated to many years even at 150°C. Above 298 K, the time required for the charge to decay to one-half its initial value is given by\log t_{1/2} = \frac{5254}{T}-\frac{771}{T}√V_{E}(s)whereT(K) is the temperature and VEis the erase voltage. The endurance of the buried-gate memory is approximately 10 K write-erase cycles and is limited by electron trapping in the insulator. A fully decoded 1024-bit memory chip was designed and fabricated.