Constantine Katsinis

A multicomputer architecture with a segmented shared bus

Abstract Single-bus multicomputer systems can support only a relatively small number of processing elements as the bus quickly becomes the communication bottleneck. Multiple-bus systems provide increased communication bandwidth and can support larger numbers of processing elements. The segmented-bus architecture is an important extension of these systems and offers even more communication bandwidth. The segmented bus contains switches between every pair of adjacent processing elements and can be dynamically segmented into smaller buses that can simultaneously connect more than one pair of processing elements. This paper examines the design of the processing elements, the mathematical modeling and the simulation of the architecture. It relates the performance of the system to the number of processing elements and the bus segmentation and allocation procedure, given a specific load.

Optoelectronic design of the simultaneous optical multiprocessor exchange bus (SOME-Bus)

Low latency, high bandwidth interconnecting networks that directly link arbitrary pairs of processing elements without contention are very desirable for parallel computers. The simultaneous optical multiprocessor exchange bus (SOME-Bus) based on a fiber optic interconnect is such a network. The SOME-Bus provides a dedicated channel for each processor for data output and thus eliminates global arbitration. Each processor can receive data simultaneously from all other processors in the system using an array of receivers. The architecture allow for simultaneous multicast and broadcast messages using several processors with zero setup time and no global scheduling. In this paper, we discuss the design of a possible opto-electronic implementation of the SOME-Bus along with an optical power budget analysis. Slant Bragg fiber grains arranged to couple light out of a fiber ribbon cable into an array of amorphous silicon detectors vertically integrated on a silicon are presented as a low cost novel means of interconnecting 10 to 120 processors.

Models of a computer architecture for processing of large numbers of images

Abstract In this paper we present statistical models, simulation results and two implementations of a multicomputer system particularly suited for processing large numbers of images and other applications involving a set of operations to be performed on a stream of data blocks. This system consists of N satellite computers and M central computers interconnected by M buses such that any satellite can communicate with any central computer. Data blocks are transferred by the central computers to the satellites where they are processed. The system performance measures are the satellite idle time and the increase in processing speed over a single computer system. We develop two models of system operation from which the idle time can be related to the statistical properties of the transfer and processing times.

Research note: Bandwidth allocation in wide-band communication networks under two types of priorities

A wide-band ISDN provides access to many different users in a shared fashion. Control of the available bandwidth allocation is necessary for efficiency and flexibility. In this paper, the system is modelled as a multiple-server multiplequeue system, where access requests require service from a random number of servers. Requests are generated by a finite number of sources. Each request is entered in a queue so that the queue index indicates the bandwidth needed by the request (in basic bandwidth units). Control of service allocation is accomplished by assigning priorities to queues. Two priority types are examined here, where relatively higher priority is assigned to requests in the smaller indexed or the larger indexed queues. When more than one request can be served due to the availability of band-width, the one with the highest priority is chosen first. The procedures that regulate the bandwidth allocation are described, and a Markov-chain based solution to the model is developed to produce the system state probabilities, and utilization and performance measures.

The development of a multi-processor personal computer in a senior computer design laboratory

This paper describes the development of a senior computer design laboratory, the purpose of which is to provide an environment where the computer design experience is as realistic and complete as possible for each student. In this laboratory, which is required for the whole senior year, students undertake the design of a CPU-based system that may be stand-alone or a part of another system. The design effort is as complete as possible, starting with a development proposal, including the hardware design and construction, and development of all necessary software in the C language, and concluding with extensive documentation. Thus, the students are encouraged to put to use a considerable amount of knowledge acquired in previous courses including computer architecture and interfacing, algorithm, languages and operating systems. They become members in groups that design components, with complexity approaching levels found in commercial products and are well prepared to become computer engineers.

A performance model of multiple resource allocation to tasks with varying demands

Abstract With the rapid development of multiprocessor systems it is possible that tasks require a number of resources (processors, buffers or communication channels) before they resume execution. This paper examines this problem of multiple resource allocation and presents the study of a system with a set of identical resources. Multiple tasks generate varying requests for a number of resources, are queued and eventually served, and then enter a state for a period of time where they generate no requests before this process is repeated. The procedures that regulate the resource allocation are described, and a Markovchain based solution to the model is developed to produce the system state probabilities, and utilization and performance measures.

Image processing experiments on a multi-microprocessor system

Abstract This paper presents the design of a multi-microcomputer which provides the basis of a system useful for processing large numbers of images. We present the architecture, the features of the operating system and experimental results. This system consists of a central computer and a number of satellite microcomputers. Communication between the central computer and each satellite is accomplished through dual-ported RAMs. It is a single bus system with a ‘star’ architecture, which under certain conditions can simulate other architectures. We have developed an operating system that allows our multicomputer system to be used in ‘user’, ‘star’, ‘queue’ and ‘pipeline’ processing modes. These processing modes allow the user to configure a powerful queueing multicomputer system. This paper presents models that predict the throughput of the system, and reports on an extensive set of experiments that are designed to test the system and verify its performance increase as a function of the number of satellites.

Message waiting time with interdependent uniform transfer and processing

Abstract This paper examines the model of a computer system where messages arrive continuously and are served by receiving some amount of processing. Both transfer and processing times depend on the length of the message, resulting in a degree of interdependence between them. Here we assume that transfer times have uniform marginal density and examine different types of joint density functions of interarrival and service times. We develop and solve a relationship between system times of successive messages, and we use the solution to develop the system state probabilities of the arrival instants.