Corey Overgaard

Field effect transistors with SrTiO3 gate dielectric on Si

SrTiO3 has been grown epitaxially by molecular beam epitaxy on Si. The capacitance of this 110 A dielectric film is electrically equivalent to less than 10 A of SiO2. This structure has been used to make capacitors and metal oxide semiconductor field effect transistors. The interface trap density between the SrTiO3 and the Si is 6.4×1010 states/cm2 eV and the inversion layer mobility is 221 and 62 cm2/V s for n- and p-channel devices, respectively. The gate leakage in these devices is two orders of magnitude smaller than a similar SiO2 gate dielectric field effect transistor.

Epitaxial oxide thin films on Si(001)

Over the years, the development of epitaxial oxides on silicon has been a great technological challenge. Amorphous silicon oxide layer forms quickly at the interface when the Si surface is exposed to oxygen, making the intended oxide heteroepitaxy on Si substrate extremely difficult. Epitaxial oxides such as BaTiO3 (BTO) and SrTiO3 (STO) integrated with Si are highly desirable for future generation transistor gate dielectric and ferroelectric memory cell applications. In this article, we review the recent progress in the heteroepitaxy of oxide thin films on Si(001) substrate by using the molecular beam epitaxy technique at Motorola Labs. Structural, interfacial and electrical properties of the oxide thin films on Si have been characterized using in situ reflection high energy electron diffraction, x-ray diffraction, spectroscopic ellipsometry, atomic force microscopy, Auger electron spectroscopy, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, high-resolution transmissi...

Self-aligned GaAs p-channel enhancement mode MOS heterostructure field-effect transistor

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga/sub 2/O/sub 3/ gate oxide, an undoped Al/sub 0.75/Ga/sub 0.25/As spacer layer, and undoped In/sub 0.2/Ga/sub 0.8/As as channel layer. The p-channel devices with a gate length of 0.6 /spl mu/m exhibit a maximum DC transconductance g/sub m/ of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality.

GaAs MESFETs fabricated on Si substrates using a SrTiO 3 buffer layer

Heteroepitaxial growth of GaAs on an Si substrate has been achieved through the use of crystalline SrTiO/sub 3/ (STO) and amorphous SiO/sub 2/ buffer layers. The buffer layers serve to accommodate some of the lattice mismatch between the substrate and the GaAs epilayers. Field-effect transistors fabricated in the GaAs epilayers show performance comparable to similar devices fabricated on GaAs substrates. The mobility in the GaAs/STO/Si sample is 2524 cm/sup 2//Vs compared to a GaAs/GaAs sample with mobility of 2682 cm/sup 2//Vs. A 0.7 /spl mu/m gate length device has I/sub d max/ of 367 mA/mm and G/sub m max/ of 223 mS/mm. These devices also have good RF performance with f/sub max/ of 14.5 GHz and class AB power density of 90 mW/mm with an associated power-added efficiency of 38% at 1.9 GHz. This RF performance is within experimental error of similar devices fabricated on GaAs substrates. Preliminary reliability results show that after 800 h at 200/spl deg/C, the GaAs/STO/Si sample showed 1.2% degradation in drain current.

Epitaxial perovskite thin films grown on silicon by molecular beam epitaxy

Thin film perovskite-type oxide SrTiO3 has been grown epitaxially on Si(001) substrate by molecular beam epitaxy. Reflection high energy electron diffraction and x-ray diffraction analysis indicate high quality SrTiO3 heteroepitaxy on Si substrate with SrTiO3(001)//Si(001) and SrTiO3[010]//Si[110]. The SrTiO3 surface is atomically as smooth as the starting substrate surface, with a root mean square roughness of 1.2 A observed by atomic force microscopy. The thickness of the amorphous interfacial layer between SrTiO3 and Si has been engineered to minimize the device short channel effect. An effective oxide thickness <10 A has been obtained for a 110 A thick dielectric film. The interface state density between SrTiO3 and Si is 6.4×1010 cm−2 eV−1, and the inversion layer carrier mobilities are 221 and 62 cm2 V−1 s−1 for n- and p-channel metal–oxide–semiconductor devices with 1.2 μm effective channel length, respectively. The gate leakage in these devices is two orders of magnitude smaller than a comparable S...

Growth and physical properties of Ga2O3 thin films on GaAs(001) substrate by molecular-beam epitaxy

We report effusive evaporation of Ga2O3 thin films on GaAs(001) substrates in a production-type molecular-beam epitaxy system. A polycrystalline Ga2O3 charge heated in a high-temperature effusion cell is used as the evaporation source. The Ga2O3–GaAs structures are characterized by atomic force microscopy (AFM), Rutherford backscattering spectroscopy (RBS), ellipsometry, and transmission electron microscopy (TEM). The Ga2O3 films are amorphous and stoichiometric by transmission electron diffraction and RBS, respectively. Under optimal growth conditions, the Ga2O3 film surface has a typical roughness of 2–3 A as revealed by AFM, while the Ga2O3–GaAs interface is atomically abrupt as confirmed by the cross-sectional TEM. Such amorphous and stoichiometric Ga2O3 oxide paves the way for GaAs gate dielectrics applications.

Development of integrated heterostructures on silicon by MBE

The semiconductor industry is facing the challenge of scaling of the gate dielectric of Si CMOS devices, which are continually being made smaller. Presently SiO/sub 2/ is being used, but at thickness below 20/spl Aring/, it suffers from high tunneling leakage current and reliability problems. Alternative high-k materials to replace SiO/sub 2/ need to be developed as soon as possible. The alkaline earth oxides such as barium strontium titanate (Ba/sub x/Sr/sub 1-x/TiO/sub 3/) have a substantially higher dielectric constant and are ideal candidates for gate dielectrics. Because of the higher dielectric constant a physically thicker layer can yield an equivalent oxide thickness of <20/spl Aring/, thereby eliminating the leakage problems experienced with ultra-thin SiO/sub 2/. These oxides also exhibit ferroelectric behavior and their use as the gate dielectric on Si can be exploited in the realization of a single transistor memory element. These types of oxides also have a number of functionalities which when combined with other types of semiconductors will enable the development of novel device applications. Molecular beam epitaxy can be used for the deposition of oxide based epitaxial layers both for Si device applications and integration of GaAs devices with silicon. The potential for increased functionality and integration of devices based on III-V semiconductors, crystalline oxides and silicon make this an attractive and promising technology.

Development of high dielectric constant epitaxial oxides on silicon by molecular beam epitaxy

Thin films of perovskite-type oxide SrTiO 3 have been grown epitaxially on Si(001) substrates using molecular beam epitaxy. Using reflection high energy electron diffraction (RHEED) we have determined the optimum growth conditions for these type of oxides directly on silicon. Also, observations of RHEED during growth and X-ray diffraction (XRD) analysis indicate that high quality heteroepitaxy on Si takes place with SrTiO 3 (001)//Si(001) and SrTiO 3 [010]//Si[110]. Thin SrTiO 3 layers grown directly on Si were used as the gate dielectric for the fabrication of MOSFET devices. An effective oxide thickness < 10 A has been obtained for a 110 A thick SrTiO 3 dielectric film with interface state density around 6.4 x 10 10 cm -2 eV -1 , and the inversion layer carrier mobilities of 220 and 62 cm 2 V -1 s -1 for NMOS and PMOS devices, respectively.

Epitaxial oxides on silicon grown by molecular beam epitaxy

Using molecular beam epitaxy, thin films of perovskite-type oxide Sr x Ba 1-x TiO 3 (0 ≤ x ≤ 1) have been grown epitaxially on Si(001) substrates. Growth parameters were determined using reflection high energy electron diffraction (RHEED). Observation of RHEED during growth and X-ray diffraction analysis indicates that high quality heteroepitaxy on Si takes place with Sr x Ba 1-x TiO 3 (001)//Si(001) and Sr x Ba 1-x TiO 3 [010]//Si[110]. Extensive atomic simulations have also been carried out to understand the interface structure and give some insights into the initial growth mechanism of the oxide layers on silicon. SrTiO 3 layers grown directly on Si were used as the gate dielectric for the fabrication of MOSFET devices. An effective oxide thickness < 10 A has been obtained for a 110 A thick SrTiO 3 dielectric film with interface state density around 6.4 x 10 10 /cm 2 /eV, and the inversion layer carrier mobilities of 220 and 62 cm 2 V/s for NMOS and PMOS devices, respectively.

Interface characterization of high-quality SrTiO3 thin films on Si(100) substrates grown by molecular beam epitaxy

Single-crystal SrTiO3 has been grown on Si(100) using molecular beam epitaxy (MBE). The growth conditions, especially at the initial stage of nucleation, have a great impact on the SrTiO3/Si interface. A regrowth of an amorphous interfacial layer as thick as 23 A has been observed and identified as a form of SiOx. This is a direct result of an internal oxidation during the growth of the STO film due to the oxygen diffusion and reaction with the silicon substrate at the interface. The optimization of the deposition process in terms of growth temperature and oxygen partial pressure has led to an interfacial layer as thin as 11 A. Metal oxide semiconductor (MOS) capacitors with an equivalent oxide thickness tox of 12 A and a leakage current of 2×10−4 A/cm2 have been obtained for a 50 A SrTiO3.