Corneel Claeys

Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

a imec, Kapeldreef 75, 3001 Heverlee, Belgium b ESAT-INSYS department, Katholieke Universiteit Leuven, 3000 Leuven, Belgium c also Post-doctoral fellow of the Fund for Scientific Research-Flanders (FWO), 1000 Brussels, Belgium d also IWT-Vlaanderen, 1000 Brussels, Belgium e Sony assignee at imec, 3001 Leuven, Belgium f Currently at IBM g Universita della Calabria, Arcavacata di Rende, Italy h Panasonic assignee at imec, 3001 Leuven, Belgium

Extraction of the lightly doped drain concentration of fully depleted SOI NMOSFETs using the back gate bias effect

We present a simple method to extract the eAective doping concentration related to the LDD (Lightly Doped Drain) regions in fully depleted SOI MOSFETs. The series resistance of an LDD structure MOSFET is composed of diAerent components, the LDD series resistance, being the dominant one. The proposed method uses the back gate voltage influence on the back interface below the LDD region. MEDICI simulations were used to support the analysis. Experimental results obtained from I‐V data were compared to the simulated results demonstrating a good agreement. 7 2000 Elsevier Science Ltd. All rights reserved.

Diffusion and solubility of dopants in germanium

The chapter focuses on the diffusion and equilibrium (maximum) solubility of dopants in germanium. Both self- and dopant diffusion are mediated by vacancies, in contrast to the situation in silicon, where interstitial, vacancy and mixed behavior can be observed. The insight in the properties of intrinsic point defects is less developed, because of experimental difficulties. To some extent, the same applies for silicon, where the vacancy and interstitial behavior is understood near the melting temperature. Currently, a similar study is undertaken for the grown-in defects during germanium crystal growth. The main problem remains that it is not clear whether one can extrapolate the high-temperature data to temperatures typically used in dopant activation and diffusion. The chapter focuses that the issue that requires further work is the non-equilibrium dopant diffusion (enhanced diffusion) that can occur during short time anneals.

1/f Noise as a Tool to Assess Fermi Level Pinning (EF) at the HfO2/poly-Si Interface in High-k n-MOSFETs

Evidence is provided that 1/f noise may be useful in the analysis of the traps responsible for Fermi level pinning at the HfO 2 /poly-Si or HfO 2 /FUSI interface in high-K n-MOSFETs. As reference devices, transistors with 1.5 nm SiON gate dielectric have been used. It is shown that adding a few (5, 10, 20) monolayers of HfO 2 enhances markedly the normalized noise magnitude in both poly-Si and FUSI devices. The 1/f noise characteristic behaves according to the number fluctuations theory and the results are interpreted in terms of trapping and de-trapping of channel carriers by defects in the gate dielectric layer. Differences in trap densities, derived from the low-frequency noise spectra are noticed at the gate/dielectric interface, which can explain the Fermi-level pinning in these devices. Additionally, it is shown that the correlated mobility fluctuations derived from the 1/f noise at larger gate voltage overdrives correlate well with the low-field mobility of the n-MOSFETs, demonstrating that the same traps in the gate dielectric are also partly responsible for the mobility degradation.

Elastic Relaxation Evaluation in SiGe/Si Hetero-Epitaxial Structures

Introduction. A key concern in strained CMOS technology is the channel stress optimization with the device scaling foreseen by the ITRS roadmap [1]. In this paper, the impact of the geometry on the stress levels and Ge content of Si1-xGex/Si hetero-epitaxial structures will be evaluated by Raman spectroscopy for several active area dimensions. The analysis will be complemented by Spectroscopic Ellipsometry (SE), High Resolution X-Ray Diffraction (HR-XRD) Nomarski optical microscopy and eventually finalized by stress simulations.

Trends and outlook

The chapter focuses on the Ge condensation technique, which is under research. Besides, the epitaxial growth of thin germanium layers on silicon is a competing technology, although the large 4% lattice mismatch, generating strain relaxation by extended defect formation has to be dealt with. The chapter also focuses on alternative device schemes, which may alleviate some of the problems like Schottky barrier Ge MOSFETs. To enhance the on current, the use of alternative channel materials like GaAs or other III – V binary and ternary compounds. The chapter also discusses the potential of 1D and 0D device structures based on Ge nanowires and quantum dots (QDs), respectively.