D. Misra

Temperature Effects on Breakdown Characteristics of High-

In this paper, the temperature dependence of time-dependent dielectric breakdown (BD) and stress-induced leakage current (SILC) of high-kappa and interfacial layers (ILs) are studied separately and in a gate stack with metal gates as the BD mechanisms of these layers are different at higher temperatures than at room temperature. As observed from the low voltage SILC, the IL initiates the gate stack BD process at elevated temperature, which is followed by the high-kappa layer. Activation energy extracted from Weibulll distribution of time-to-BD (T BD) data from high-kappa layer further suggests that the gate stack BD occurs when high- kappa layer ultimately breaks down.

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A CMOS magnetic field sensor array that can be implemented along with analog and digital signal processing circuitry in the form of a single integrated circuit for instrumentation or measurement is discussed. The design realizes a single sensor device through interconnection of a few n-channel magnetic-field-sensitive MOSFETs (MAGFETs) in one circuit. The experimental measurements suggest that the interconnection, which forms a parallel tree structure, provides a higher relative sensitivity compared to that of the genealogical tree structure reported previously. The parallel structure eliminates the additional power supply and body effects and takes less integration area. The relative sensitivity of the CMOS sensor device with an array of five split-drain MAGFETs is 77 mA/A/T. >

Gate Dielectrics With Metal Gates

It is shown that the gate material has a strong impact on the low‐frequency (LF) 1/f noise of silicon nMOSFETs with a 1.5 nm SiON gate dielectric. Highest noise is observed for transistors with an n‐type polysilicon gate, compared with their counterparts having a metal (TaN) or a fully nickel‐silicided polysilicon gate (NiSi). The differences are particularly pronounced in strong inversion (high gate voltage VGS). The observations cannot be explained readily in the frame of the standard correlated‐mobility fluctuations theory. They point rather to the impact of the charges/traps at the gate‐dielectric interface, which are better screened in case of a metal gate. At the moment, one can only speculate on the origin of the LF fluctuations, giving rise to the higher noise in strong inversion. One hypothesis is that the image charge at the gate induced by a filled oxide trap contributes to excess scattering in the channel.

A novel CMOS magnetic field sensor array

This work investigates the interface properties in a metal oxide semiconductor capacitor device with a 3 nm HfAlO/0.5 nm SiO2/Si stacks prepared by various processing conditions. Different Al doping, different postannealing temperatures, and different deposition steps and stacks were considered. Equivalent oxide thickness and flat band voltage (VFB) were obtained from capacitance–voltage measurements. After the measurement, a simple approach was used to correct the error introduced by the series resistance Rs associated with the substrate and contact while carefully monitoring the impact of the tunneling current. The interface state density (Dit) was calculated by the conductance method, and it was observed that the Dit is dependent on the structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit ( 2.76×1011 eV−1cm−2) whereas tetragonal HfO2 has the highest Dit ( 1.27×1012 eV−1cm−2). The Dit values of other structures are within the range of observed highest and lowest values.

Impact of Gate Material on Low‐frequency Noise of nMOSFETs with 1.5 nm SiON Gate Dielectric: Testing the Limits of the Number Fluctuations Theory

In three-dimensional (3-D) integrated magnetic sensor design, cross-axis sensitivities among the various components of the magnetic field have been a problem. In this brief it is demonstrated that complete elimination of the cross-sensitivity is possible if a 3-D magnetic sensor is implemented in BiCMOS technology. A compact device structure is designed to detect the three components of the magnetic field vector by placing a split-collector magnetotransistor and a split-drain MOSFET adjacent to each other. Measured sensitivities of the sensor are presented. >

Oxide structure-dependent interfacial layer defects of HfAlO/SiO2/Si stack analyzed by conductance method

The authors report on the achievement of full-color nanowire light-emitting diodes (LEDs), with the incorporation of InGaN/AlGaN nanowire heterostructures grown directly on the Si (111) substrates by molecular beam epitaxy. Multiple color emission across nearly the entire visible wavelength range can be realized by varying the In composition in the InGaN quantum dot active region. Moreover, multiple AlGaN shell layers are spontaneously formed during the growth of InGaN/AlGaN quantum dots, leading to the drastically reduced nonradiative surface recombination, and enhanced carrier injection efficiency. Such core–shell nanowire structures exhibit significantly increased carrier lifetime and massively enhanced photoluminescence intensity compared to conventional InGaN/GaN nanowire LEDs. A high color rendering index of ∼98 was recorded for white-light emitted from such phosphor-free core–shell nanowire LEDs.

Elimination of cross sensitivity in a three-dimensional magnetic sensor

This paper has demonstrated a high-quality HfO2-based gate stack by depositing atomic-layer-deposited HfAlOx along with HfO2 in a layered structure. In order to get a multifold enhancement of the gate stack quality, both Al percentage and distribution were observed by varying the HfAlOx layer thickness and its location in the gate stack. It was found that <; 2% Al/(Al + Hf)% incorporation can result in up to 18% reduction in the average EOT along with up to 41% reduction in the gate leakage current, as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increased the interface state density Dit. When devices were stressed in the gate injection mode at a constant voltage stress, the dielectrics with Al/(Hf+Al)%<;2% showed resistance to stress-induced flatband voltage shift ΔVFB, and stress-induced leakage current. The time-dependent dielectric breakdown characteristics showed a higher charge to breakdown and an increase in the extracted Weibull slope β, which further confirms an enhanced dielectric reliability for devices with <; 2% Al/(Al + Hf)%.

Controlling color emission of InGaN/AlGaN nanowire light-emitting diodes grown by molecular beam epitaxy

In this work, the progressive breakdown (PBD) phase and non-Weibull final failure distributions of multi layer high-k and SiO2 gate dielectric were investigated by voltage ramp stress (VRS) technique. A new hybrid two-stage constant voltage stress/voltage ramp stress methodology was developed to exclusively evaluate the PBD phase. Then the VRS technique was applied to investigate the non-Weibull failure distribution at a specified current (IFAIL) with large sample-size (∼1000) experiments. An excellent agreement was achieved in both cases in comparison with the conventional CVS technique, thus demonstrates that VRS is an effective technique to replace the CVS technique for investigation of post-BD and non-Weibull statistics in both SiO2 and high-k dielectrics.

Multilayered ALD HfAlO x and HfO 2 for High-Quality Gate Stacks

By studying systematically the breakdown mechanisms of HfO 2 and interfacial SiO 2 separately in this work, we have demonstrated that defect generation in the interfacial SiO 2 layer seems to be the leading breakdown mechanism in the metal/high-K/interfacial layer/Si gate stack. The individual breakdown characteristics of HfO 2 , without any interfacial layer using a metal-insulator-metal capacitor, and an in situ steam-grown SiO 2 metal-oxide-semiconductor capacitor with identical thicknesses and growth conditions, were compared with the gate stack characteristics. The breakdown behavior and stress-induced leakage current measurements suggest that charge trapping and stress-induced trap formation in the interfacial layer continues to be the soft spot for gate stack breakdown.

Investigation of progressive breakdown and non-Weibull failure distribution of high-k and SiO 2 dielectric by ramp voltage stress

This work examines the inherent asymmetry on breakdown characteristics of the interfacial layer (IL) and high-K layer in the overall gate-stack breakdown. Ramped and constant voltage stresses were applied on atomic-layer-deposited TiN/HfO 2 /SiO 2 gate stacks. Under ramped stress when a thin high-K layer (≤3.3 nm) is used, IL is responsible for the overall gate-stack breakdown; otherwise, the breakdown is initiated by the high-K layer. Under constant voltage stress the gate stack went through many degradation mechanisms, such as charge trapping and defect generation, soft breakdown, progressive breakdown, and finally hard breakdown. In addition, when the breakdown field of ILs grown under various process conditions was compared, it was observed that for a fixed IL thickness, breakdown field does not depend on predeposition surface treatment; rather, it is a function of the quality of IL. Stress-induced leakage current was also studied to correlate with the breakdown behavior.