Craig A. Hornbuckle
Semtech
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Publication
Featured researches published by Craig A. Hornbuckle.
optical fiber communication conference | 2009
Kun-Wook Chung; Samuel Steidl; Thomas W. Krawczyk; Roger Miller; Song Shang; Taqi Mohiuddin; Jay Cormier; Craig A. Hornbuckle
The required features of SerDes chips for 100Gbps Ethernet and OTN optical data transmission are discussed. As a baseline technology for 100Gbps SerDes, 40Gbps DPQSK serializer chip performance is presented.
custom integrated circuits conference | 2003
Thomas W. Krawczyk; Samuel A. Steidl; Richard Alexander; James Pulver; Gary Kowalski; Craig A. Hornbuckle; David A. Rowe
A 16:1 multiplexer and 1:16 demultiplexer, designed using a 0.18 /spl mu/m SiGe BiCMOS process, operates at data rates between 39.8 Gb/s and 43.1 Gb/s. The demultiplexer features an integrated CDR (clock and data recovery) with an input sensitivity of 25 mV at 40 Gb/s and 40 mV at 43 Gb/s. The multiplexer has an integrated CMU (clock multiplier unit) and an output voltage swing of 1 Vp-p differential with 165 fs rms jitter. Both chips are SFI-5 compliant. The multiplexer and demultiplexer dissipate 10 W and 4.7 W of power, respectively, using supply voltages of -3.6 V and 1.2 V (or 1.8 V).
optical fiber communication conference | 2002
Samuel Steidl; David A. Rowe; Thomas W. Krawczyk; P. Wong; A. Tam; Craig A. Hornbuckle
TIAs were designed with transimpedance gains of 230 /spl Omega/ and 240 /spl Omega/, with corresponding bandwidths of 30 GHz and 29 GHz, respectively. Because the simulated results in the 50 /spl Omega/ test environment match reasonably well with the measured results, it is expected that the TIA performance, when packaged with an appropriate photodiode, will improve, as the simulated results for a TIA with a photodiode indicate.
compound semiconductor integrated circuit symposium | 2010
Thomas W. Krawczyk; Todd Cooper; Samuel Steidl; Peter F. Curran; Masashi Yamagata; Song Shang; Tony Liu; James Pulver; Cliff Duong; Zuoding Wang; Darren Walworth; Craig A. Hornbuckle; David A. Rowe
A 4 by 28.3 to 10 by 11.32 Gb/s SFI-S compliant two chip SerDes for 100 Gb/s applications was fabricated using IBMs SiGe 130 nm 8HP process (210 GHz fT). The Multiplexer receives 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s, and outputs four lanes at 28.3 Gb/s, with a maximum output of 1.2 Vpp differential. The Demultiplexer receives four channels at 28.3 Gb/s, recovers clock and data with a sensitivity of 40 mV, and outputs 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s.
Archive | 2009
Jean-Pierre Joseph Tracy Cole; David A. Rowe; Craig A. Hornbuckle
Archive | 2007
Craig A. Hornbuckle; David A. Rowe; Thomas W. Krawczyk; Samuel Steidl; Inho Kim
Archive | 2008
Craig A. Hornbuckle; David A. Rowe
Archive | 2004
David A. Rowe; Craig A. Hornbuckle; Matthew D Pope
Archive | 2006
David A. Rowe; Craig A. Hornbuckle; Matthew D Pope
Archive | 2009
Kevin William Glass; Craig A. Hornbuckle; C. Gary Nilsson