David A. Rowe

A 39.8Gb/s to 43.1Gb/s SFI-5 compliant 16:1 multiplexer and 1:16 demultiplexer for optical communication systems

A 16:1 multiplexer and 1:16 demultiplexer, designed using a 0.18 /spl mu/m SiGe BiCMOS process, operates at data rates between 39.8 Gb/s and 43.1 Gb/s. The demultiplexer features an integrated CDR (clock and data recovery) with an input sensitivity of 25 mV at 40 Gb/s and 40 mV at 43 Gb/s. The multiplexer has an integrated CMU (clock multiplier unit) and an output voltage swing of 1 Vp-p differential with 165 fs rms jitter. Both chips are SFI-5 compliant. The multiplexer and demultiplexer dissipate 10 W and 4.7 W of power, respectively, using supply voltages of -3.6 V and 1.2 V (or 1.8 V).

Superconducting direct digital synthesizer

Communications transmitters, receivers, radar applications, and related test equipment require precise control over generated frequencies which can be provided by digital synthesis. Superconductivity technology offers to greatly improve the operational frequency range at a tiny fraction of the power of present GaAs and Si digital frequency synthesizers, an important consideration for systems with multiple receiver elements and satellite applications. We designed, fabricated, and tested a digital superconducting frequency synthesizer on a 1-cm square substrate in niobium technology and tested at 4 Kelvin. The chip contains a 12-bit pipelined MVTL incremental phase accumulator (simple expansion to 32 bits achieves one part in 4.3/spl times/10/sup 9/ frequency resolution). The most significant 10-bits of the accumulated phase proceed to a Sine ROM which is based on SQUID cells and employs data compression to minimize circuit size. An 8-bit ROM output word proceeds to a superconducting D/A converter to construct the analog output waveform which updates each clock cycle. We have operated the entire superconducting synthesizer above 1 GHz. Our performance goal with present fabrication technology is /spl ges/4 GHz operation.

A transimpedance amplifier for OC-768 applications designed using a SiGe HBT BiCMOS technology

TIAs were designed with transimpedance gains of 230 /spl Omega/ and 240 /spl Omega/, with corresponding bandwidths of 30 GHz and 29 GHz, respectively. Because the simulated results in the 50 /spl Omega/ test environment match reasonably well with the measured results, it is expected that the TIA performance, when packaged with an appropriate photodiode, will improve, as the simulated results for a TIA with a photodiode indicate.

A 4 by 28.3 Gb/s SFI-S SerDes in 130 nm SiGe

A 4 by 28.3 to 10 by 11.32 Gb/s SFI-S compliant two chip SerDes for 100 Gb/s applications was fabricated using IBMs SiGe 130 nm 8HP process (210 GHz fT). The Multiplexer receives 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s, and outputs four lanes at 28.3 Gb/s, with a maximum output of 1.2 Vpp differential. The Demultiplexer receives four channels at 28.3 Gb/s, recovers clock and data with a sensitivity of 40 mV, and outputs 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s.