Craig Child

Metal wiring critical dimension shrink using ALD spacer in BEOL sub-50nm pitch

In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple patterning (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. In this paper, we demonstrate metal critical dimension (CD) shrinkage using atomic layer deposition (ALD) enabled spacer layer to achieve sub-50 nm pitch. ALD spacer thickness is identified as the crucial parameter to achieve target CD. An optimization study correlating oxide thickness, final CD and electrical yield is presented. An optimized recipe that results in 50% shrinkage is identified with good electrical yield.

Electron scattering at interfaces in nano-scale vertical interconnects: A combined experimental and ab initio study

We present a combined theoretical and experimental study on the electron transport characteristics across several representative interface structures found in back-end-of-line interconnect stacks for advanced semiconductor manufacturing: Cu/Ta(N)/Co/Cu and Cu/Ta(N)/Ru/Cu. In particular, we evaluate the impact of replacing a thin TaN barrier with Ta while considering both Co and Ru as wetting layers. Both theory and experiment indicate a pronounced reduction in vertical resistance when replacing TaN with Ta, regardless of whether a Co or Ru wetting layer is used. This indicates that a significant portion of the total vertical resistance is determined by electron scattering at the Cu/Ta(N) interface. The electronic structure of these nano-sized interconnects is analyzed in terms of the atom-resolved projected density of states and k-resolved transmission spectra at the Fermi level. This work further develops a fundamental understanding of electron transport and material characteristics in nano-sized interconnects.

Cu seed optimization for minimum pitch wiring in 10nm and beyond

Technology scaling necessitates interconnect structures (metal and vias) in the back end of the line (BEOL) module to sub 50nm pitch. This presents significant challenges to the conventional metallization scheme, consisting of liner, seed deposition and Cu plating. Seed layer deposition particularly is quite challenged because of increasing aspect ratio. Additionally, the presence of hard mask in the local metal interconnects (Mx) induces undercut in the metal line profile making metallization even more challenging. The consequence is a significant increase in metal voiding defects as compared to previous technology nodes. Hence the conventional metallization scheme requires reengineering to suit the needs of advanced nodes. In this paper, a systematic approach to tune and optimize the copper seed deposition and its effect on metal electrical yield is presented. Through design of experiments (DOE) the metal open yield (post high temperature anneal-hammer test) improved from less than 10% to greater than 50% for the optimized seed deposition recipe (post stress). The optimized recipe reduced the void related defects responsible for the lower metal open yield. Results from current ramp test, via chain yield and electromigration data will be presented for the optimized seed recipe.

Planarity considerations in SADP for advanced BEOL patterning

In this paper, the impact of gap-fill planarity on Multi-Self-Aligned Block, SADP (self-aligned double patterning) process for advanced optical technology nodes (7 nm/5 nm) interconnects was studied through process emulations. This study specifically focuses on the insertion of an etch stop layer (ESL) between two coatings of organic planarization layer (OPL), referred to as the tri-layer PM (pattern mask), which enables a thinner OPL for pattern transfer while adding topography correction for non-mandrel block patterning processes. This scheme reduces pillar aspect ratio for improved CD control and flop-over mitigation, as well as topography correction to mitigation false metal patterns in field regions. However, ESL could cause CD variation if it was deposited on the sidewall of spacer where it is a function of the conformality of ESL deposition.

Segment removal strategy in SAQP for advanced BEOL application

In this paper, a strategy of performing segment removal in an SAQP (self-aligned quadruple patterning) and its implication on interconnect parasitic capacitance are reported. In order to reduce the cost and process complexity, through process emulations, this study specifically focuses on not introducing additional lithography step(s) or material to the conventional SADP (self-aligned double patterning) integration. Four SAQP process integrations are demonstrated to selectively remove dummy lines in between the signal lines from sea of lines, as a result, the line to line capacitance can be reduced. The conventional non-mandrel block lithography step will only remove every other line. Typically, to remove more lines requires an additional hard mask layer and a first non-mandrel block lithography step where the line to line capacitance can be further reduced. However, in this study, a double spacer transfer scheme is proposed to achieve the same final structure but without the additional hard mask layer and lithography step. Therefore, this could be another option for 7 nm or 5 nm process integration of BEOL interconnects.

Nested interconnect macro electrical yield improvement for advanced triple patterning integration

For metal pitches below 50nm, triple patterning (LELELE) integration is utilized in most advanced technologies to build the Cu interconnect. This integration relies on etch to shrink to the target critical dimension. As a result of high iso-dense bias in conventional etch process, nested serpentine structures formed by different metal colors show massive shorts that limit defect density yield. In this paper, several approaches in improving the iso-dense bias, as well as improving the nested serpentine electrical yield will be discussed.

10nm local interconnect challenge with iso-dense loading and improvement with ALD spacer process

10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel ALD spacer-shrink process which improves iso-dense CD difference by 50%.

Optimization of wet clean and its impact on sub-50 nm pitch BEOL yield

In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple pattering (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. This scenario has imposed increased demands on many of the semiconductor processes involved in the fabrication of integrated circuits. One such process is the wet clean process. In this paper, a direct correlation between clean chemistry and metal/via electrical yield is shown in M1 module of 10 nm technology node. Line and via open yield improved 10X upon adding iso propyl alcohol (IPA) to the standard dilute hydrofluoric acid (dHF) aqueous solution. IPA acts as an inhibitor, and reduces the surface tension, thus preventing over-aggressive etch and displacement of pattern structures during the clean process.

Optimization of porous ultra low-κ dielectrics (κ ≤ 2.55) for 28nm generation

There is an ongoing need in the microelectronics industry to increase circuit density in multilevel back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. One way to maintain capacitance-resistance (RC) performance, without de grading yield or reliability is through introduction of porous ultra low-κ materials (ULK) as interlevel dielectrics (ILD). This paper presents the ability to tune ULK films through simple processing optimization steps to meet the specific integration requirements. Balancing composition of the film to minimize damage needs to be coupled with improving mechanical integrity for packing compatibility.