Craig Huffman

Carbonized layer formation in ion implanted photoresist masks

Abstract The formation of a carbonized layer in positive photoresist after high dose ion implants has been studied as a function of the implant parameters. In this study SEM observations of the carbonized layer were used to confirm that the physical scattering characteristics of the ions within the photoresist determine the extent to which the carbonization, or increase of the relative carbon concentration, can occur. The thickness of the carbonized layer was found to be directly dependent on the energy and atomic species of the ions, and to be relatively independent of the ion beam current and the total ion dose. The role of the ion dosage in the formation of the carbonized layer is discussed, and the wet and dry etch characteristics of the carbonized layer are presented.

Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.

Thermal budgeting in a double level metal process with CVD tungsten as first metal

The high-temperature stability of CVD tungsten (W) interconnects over TiSi/sub 2/-clad diffusions was tested up to 700 degrees C. A sputtered 10 wt.% Ti in W sticking layer was used to nucleate the W. Contact resistance was stable at the highest temperatures, and measured to be <0.01 mu ohm/cm/sup 2/. Junction leakage decreased from approximately 50 na/cm/sup 2/ to <5 na/cm/sup 2/ on 700 degrees C annealing of both p/sup +//n/sup -/ and n/sup +//p/sup -/ diodes. Apart from the expected benefits from CVD blanket W of excellent contact filling and high reliability, it is concluded that the results show an opportunity for higher temperature post-metal processing than can be realized for Al alloys when used with the TiSi/sub 2/ transistor cladding process. The results obtained point to the possibility of higher temperature oxide depositions than are now allowed following metal processing, to enhance the conformality of the interlevel insulators and reduce the tendency for void formation.<<ETX>>

A novel, shallow-trench-isolated, planar, N+SAG FAMOS transistor for high-density nonvolatile memories

The authors report the fabrication, for the first time, of a shallow-trench isolated (less than 1 mu m deep) planarized, floating-gate avalanche injection MOS (FAMOS) transistor with n/sup +/ bitlines self-aligned to gate (n/sup +/ SAG). Key to the planar process is the self-alignment of the buried n/sup +/ diffusions (bitlines) to the floating gate of the FAMOS transistor and the deposition over these diffusions of a low-temperature, conformal CVD (chemical vapor deposition) oxide. An oxide-resist etchback process was used to planarize the buried n/sup +/ CVD oxide. Trench etching was done immediately after definition of the stacked polysilicon gates. Using an anisotropic etch for single-crystal silicon, trenches with a 0.75 mu m depth were made in the bitline isolation areas of the planar devices. The trenches were then refilled with thermal and LPCVD (liquid-phase CVD) SiO/sub 2/. Characterization of the planar EPROM (erasable programmable read-only memory) cell shows that the shallow trench between bitlines has improved their isolation characteristics. An increase in programming efficiency of as much as 30% at a pulse width of 1 ms was observed in the case of the shallow-trench-isolated FAMOS. Additional data indicate the possibility of programming the trench isolated cell at drain voltages lower than the present 12.5 V, thus reducing high voltage requirements. >