Cristian Cismaru

Formulations and a Computer-Aided Test Method for the Estimation of IMD Levels in an Envelope Feedback RFIC Power Amplifier

This paper presents new formulations, together with an efficient computer-aided test approach intended for radio frequency integrated circuit power amplifiers (PAs), allowing the estimation of linearity requirements for the circuit blocks typically found in the error signal path of an envelope feedback amplifier. The formulations are based on a three-tone excitation, allowing analysis of intermodulation distortion (IMD) within the feedback system using parameterized peak-to-average envelope voltage. They are also based on a fifth-degree representation, and may be extended to higher degrees of nonlinearities in the RF PA block, enabling IMD analysis of envelope feedback amplifiers at low power. The approach proposed in this paper circumvents the difficulty of measuring error signals during closed-loop operation for troubleshooting purposes. This approach is also very useful for computer-aided test setups intended for development work independent of the often idealized circuit simulation environment.

Measuring seam/crack formation in interconnect metallization

Abstract Low cost processes, in both GaAs and Silicon, often use non-planar interconnect metals. While very efficient in simplifying processes, seam (more commonly called “crack”) formation due to inter-level dielectric topologies can (1) cause significant thinning in the metallization, impacting the reliability and (2) act as process defects that reduces circuit yield. To better understand and monitor crack formation, we used a series of test structures to develop an electrical test allowing crack formation to be characterized. We confirmed our results with cross sections. The methodology presented here is also used to characterize new process steps or processes to verify the new process make cracking worse. In the first application of this method, it highlighted a potential cracking issue, preventing it from propagating into production.

InGaP-GaAs HBT Statistical Modeling for RF Power Amplifier Designs

A simple statistical modeling methodology is presented for InGaP-GaAs HBTs devices and RF power amplifier circuits. The modeling approach utilizes in-line electrical parameter control data and DOE method to establish relationships between important material and model parameters. The key considerations of parameter selection are given and essential connections from device physics to model parameters are described. This statistical model allows designs that are robust to process variations and provide circuit designers with a method to de-bug design issues that can result from device variations. The authors show the background that supports this approach and demonstrate its application at both a device and circuit level

A Method for Yield and Scaling Characterization of FETs in an InGaP/GaAs Merged HBT-FET (BiFET) Technology

A method for FET yield and scaling analysis of the FET device in a merged FET-HBT GaAs process (BiFET) is described. Using the current-source configuration of a depletion mode FET, a number of devices were connected and stacked together in series and then this stack was replicated into multiple columns; this allows a yield and/or scaling test over a relatively large area. With just one landing of a dc probe, any single device in a 210 device set that has an IDSS that is out of spec will cause a failure that can be quickly identified and its location mapped. In a second type of analysis, a quick measure of device-to-device matching and scaling across a mix of individual and series devices are taken such that any discrepancies can be documented. The matching tests are performed either as side-by-side comparisons or measured over multiple test points as device area is increased progressively. With help from the new structures the root cause of a metal-semiconductor interface problem was quickly identified. It is believed that future BiFET technology iterations will be able to be qualified with fewer development lots and yield targets will be able to be met ahead of schedule.

Prospects for a BiCFET III-V HBT Process

While complementary FETs are routinely available in BiCMOS processes, the successful integration of HBTs with complementary FETs has not been reported. In this work, we demonstrate a material structure and process capable of allowing HBTs plus n and p-channel MESFETs. We report on the DC and AC characteristics of the HBT and the p-FET DC performance. The n-FET is unaffected by this material design.