D. Brian Larkins

Scalable work stealing

Irregular and dynamic parallel applications pose significant challenges to achieving scalable performance on large-scale multicore clusters. These applications often require ongoing, dynamic load balancing in order to maintain efficiency. Scalable dynamic load balancing on large clusters is a challenging problem which can be addressed with distributed dynamic load balancing systems. Work stealing is a popular approach to distributed dynamic load balancing; however its performance on large-scale clusters is not well understood. Prior work on work stealing has largely focused on shared memory machines. In this work we investigate the design and scalability of work stealing on modern distributed memory systems. We demonstrate high efficiency and low overhead when scaling to 8,192 processors for three benchmark codes: a producer-consumer benchmark, the unbalanced tree search benchmark, and a multiresolution analysis kernel.

Application of the cognitive apprenticeship framework to a middle school robotics camp

This paper details the development and implementation of a summer robotics camp for middle school children. The Cognitive Apprenticeship (CA) model is used as the framework for developing the camp. Specifically, methods such as modeling, coaching, scaffolding, articulation, reflection, and exploration are integrated throughout the camp structure. Activities include the use of an engineering notebook, debugging logs, and various cognitive challenges, all supervised by a team of expert mentors. During the two-week summer camp, participants realized a positive shift in attitudes towards science, developed common engineering design skills, and showed increased proficiency in the reasoning pattern of isolation of variables. The CA framework, in conjunction with robotics are an excellent way to build interest in STEM and develop skills in engineering, science, and computational thinking.

Global trees: a framework for linked data structures on distributed memory parallel systems

This paper describes the Global Trees (GT) system that provides a multi-layered interface to a global address space view of distributed tree data structures, while providing scalable performance on distributed memory systems. The Global Trees system utilizes coarse-grained data movement to enhance locality and communication efficiency. We describe the design and implementation of GT, illustrate its use in the context of a gravitational simulation application, and provide experimental results that demonstrate the effectiveness of the approach. The key benefits of using this system include efficient shared-memory style programming of distributed trees, tree-specific optimizations for data access and computation, and the ability to customize many aspects of GT to optimize application performance.

Introductory computational science using MATLAB and image processing

Abstract We describe a new course designed to introduce engineering students to computational thinking. One of the most significant challenges in teaching an introductory-level applied computing course is that students are not expected to have substantial math and science experience. To address this, we have developed exercises which use edge detection and basic image processing to motivate the use of programming MATLAB in a non-trivial scientific application. MATLAB is a popular high-level programming language and environment which supports a wide range of computational science applications. MATLAB has strong support for operating on image data, which allows us to balance solving practical engineering problems with basic core concepts of computer science such as functional abstraction, conditional execution, and iteration.

Improving data locality for irregular partitioned global address space parallel programs

This paper describes a technique for improving the data reference locality of parallel programs using the Partitioned Global Address Space (PGAS) model of computation. One of the principal challenges in writing PGAS parallel applications is maximizing communication efficiency. This work describes an on-line technique based on run-time data reference profiling to organize fine-grained data elements into locality-aware blocks suitable for coarse-grained communication. This technique is applicable to parallel applications with large, irregular, pointer-based applications. The described system can perform automatic data relayout using the locality-aware mapping with either iterative (timestep) based applications or as a collective data relayout operation. An empirical evaluation of the approach shows that the technique is useful in increasing data reference locality and improves performance by 10-17% on the SPLASH-2 Barnes-Hut tree benchmark.

Integrating digital logic design and assembly programming using FPGAs in the classroom

Rising Field Programmable Gate Array (FPGA) market volumes combined with increasing industrial popularity have driven prices down and improved capability to the point that FPGA hardware and development environments afford academia the unique opportunity to embrace this technology not only in specialized graduate-level courses, but also across many of the courses of a traditional undergraduate computer science curriculum. We have begun adapting several of our undergraduate computer science courses and associated laboratories to make use of FPGAs as a common platform of instruction. In this paper, we illustrate how to make use of FPGAs in courses that cover digital logic design and assembly programming while discussing some of the pros and cons of their use. We also provide a detailed discussion of a laboratory project that integrates both assembly programming as well as digital logic design in such a way that allows the student to perform a trade-off analysis between using software in the place of a purely hardware-based solution to a common interfacing problem. We conclude with an analysis of preliminary data gathered via student surveys and find that the results support the use of FPGA-based platforms in the undergraduate classroom. By making use of FPGA-based systems, not only are students exposed to a technology that is becoming much more prevalent in industry, they also benefit from the dovetailing of concepts and shorter learning curves between courses that come from making use of a common target platform.

Extending a message passing runtime to support partitioned, global logical address spaces

Partitioned Global Address Space (PGAS) parallel programming models can provide an efficient mechanism for managing shared data stored across multiple nodes in a distributed memory system. However, these models are traditionally directly addressed and, for applications with loosely-structured or sparse data, determining the location of a given data element within a PGAS can incur significant overheads. Applications incur additional overhead from the network latency of lookups from remote location resolution structures. Further, for large data, caching such structures locally incurs space and coherence overheads that can limit scaling. We observe that the matching structures used by implementations of the Message Passing Interface (MPI) establish a separation between incoming data writes and the location where data will be stored. In this work, we investigate extending such structures to add a layer of indirection between incoming data reads and the location from which data will be read, effectively extending PGAS models with logical addressing.

Targeting FPGA-based processors for an implementation-driven compiler construction course

This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the significant challenges in teaching using modern hardware platforms is the inordinate complexity of commonly used systems. To avoid this, many compiler courses target a less complex platform implemented via a simulator or a higher-level virtual or abstract hardware platform. To avoid the complexity of a modern superscalar multicore architecture and to improve the kinesthetic experience of students implementing the course compiler, we have provided a framework and runtime support for using an FPGA-based RISC CPU as the target for the compiler backend. Using this system allows students to leverage knowledge gained in earlier organization and architecture classes using the same system, while also providing a hands-on active learning component at the completion of the compiler implementation.

Efficient Runtime Support for a Partitioned Global Logical Address Space

Many HPC applications have successfully applied Partitioned Global Address Space (PGAS) parallel programming models to efficiently manage shared data that is distributed across multiple nodes in a distributed memory system. However, while the flat addressing model provided by PGAS systems is effective for regular array data, it renders such systems difficult to use with loosely-structured or sparse data. This work proposes a logically addressed PGLAS model that naturally supports a variety of data models through the automatic mapping of an application-defined key space onto the underlying distributed memory system. We present an efficient implementation of the PGLAS model built atop a parallel distributed hash table (PDHT) and demonstrate that this model is amenable to offloading using the Portals 4 network programming interface. We demonstrate the effectiveness of PDHT using representative applications from the computational chemistry and genomics domains. Results indicate that PGLAS models such as PDHT provide a promising new method for parallelizing applications with non-regular data.

E-Assess: A Web-Based Tool for Coordinating and Managing Program Assessment (Abstract Only)

This poster describes the operation and implementation of the E-Assess web-based program assessment tool. The E-Assess tool provides a centralized management system for generalized program assessment and has been used to support ABET program assessment within the CS/IS department at Coastal Carolina University for the past two years. This system defines multiple roles for several different assessment activities -- allowing individual faculty to operate independently, yet still providing an always up-to-date view of the process to assessment coordinators. Coordinators provide mappings between overall program objectives and specific measurement points across the curriculum. At the conclusion of a class, the instructor enters the assessment measures specific to the course. When all course data has been added, the E-Assess system automatically compiles the overall assessment data into summary reports that are used to evaluate program progress and to inform the continuous improvement process.