William M. Jones

Impact of sub-optimal checkpoint intervals on application efficiency in computational clusters

As computational clusters rapidly grow in both size and complexity, system reliability and, in particular, application resilience have become increasingly important factors to consider in maintaining efficiency and providing improved computational performance over predecessor systems. One commonly used mechanism for providing application fault tolerance in parallel systems is the use of checkpointing. By making use of a multi-cluster simulator, we study the impact of sub-optimal checkpoint intervals on overall application efficiency. By using a model of a 1926 node cluster and workload statistics from Los Alamos National Laboratory to parameterize the simulator, we find that dramatically overestimating the AMTTI has a fairly minor impact on application efficiency while potentially having a much more severe impact on user-centric performance metrics such a queueing delay. We compare and contrast these results with the trends predicted by an analytical model.

Application monitoring and checkpointing in HPC: looking towards exascale systems

As computational cluster computers rapidly grow in both size and complexity, system reliability and, in particular, application resilience have become increasingly important factors to consider in maintaining efficiency and providing improved compute performance over predecessor systems. One commonly used mechanism for providing application fault tolerance in parallel systems is the use of checkpointing. We demonstrate the impact of sub-optimal checkpoint intervals on application efficiency via simulation with real workload data. We find that application efficiency is relatively insensitive to error in estimation of an applications mean time to interrupt (AMTTI), a parameter central to calculating the optimal checkpoint interval. This result corroborates the trends predicted by previous analytical models. We also find that erring on the side of overestimation may be preferable to underestimation. We further discuss how application monitoring and resilience frameworks can benefit from this insensitivity to error in AMTTI estimates. Finally, we discuss the importance of application monitoring at exascale and conclude with a discussion of challenges faced in the use of checkpointing at such extreme scales.

Towards Building Resilient Scientific Applications: Resilience Analysis on the Impact of Soft Error and Transient Error Tolerance with the CLAMR Hydrodynamics Mini-App

In this paper, we present a resilience analysis of the impact of soft errors on CLAMR, a hydrodynamics miniapp for high performance computing (HPC). Leveraging the conservation of mass law, we design a fault detection mechanism and checkpoint/restart fault tolerance approach to enhance the resilience of CLAMR. Overall, our approach can detect up to 88.3% of faults that propagate into SDC or crashes with minimal (less than 1%) overhead for the optimal configuration. We show that CLAMRs fault-tolerance depends on when a fault is injected into the simulation and we also evaluate the frequency of detection and checkpointing on performance.

Fault Injection Experiments with the CLAMR Hydrodynamics Mini-App

In this paper, we present a resilience analysis of the impact of soft errors on CLAMR, a hydrodynamics mini-app for high performance computing (HPC). We utilize F-SEFI, a fine grainedfault injection tool, to inject faults into the kernel routines of CLAMR. We demonstrate visually the impact of these faults as they are either benign (have no impact on the results), cause silent data corruption (SDC), or cause the application to crash due to instabilities. We quantify the probability that an injected fault will cause CLAMR to transition to one of the above three states using F-SEFI. Finally, we explore the relationship between the applications fault characteristics and when the fault is injected in simulation time. Overall, we find that 17% and 24% of the faults propagate into SDC and crashes respectively.

Integrating digital logic design and assembly programming using FPGAs in the classroom

Rising Field Programmable Gate Array (FPGA) market volumes combined with increasing industrial popularity have driven prices down and improved capability to the point that FPGA hardware and development environments afford academia the unique opportunity to embrace this technology not only in specialized graduate-level courses, but also across many of the courses of a traditional undergraduate computer science curriculum. We have begun adapting several of our undergraduate computer science courses and associated laboratories to make use of FPGAs as a common platform of instruction. In this paper, we illustrate how to make use of FPGAs in courses that cover digital logic design and assembly programming while discussing some of the pros and cons of their use. We also provide a detailed discussion of a laboratory project that integrates both assembly programming as well as digital logic design in such a way that allows the student to perform a trade-off analysis between using software in the place of a purely hardware-based solution to a common interfacing problem. We conclude with an analysis of preliminary data gathered via student surveys and find that the results support the use of FPGA-based platforms in the undergraduate classroom. By making use of FPGA-based systems, not only are students exposed to a technology that is becoming much more prevalent in industry, they also benefit from the dovetailing of concepts and shorter learning curves between courses that come from making use of a common target platform.

Targeting FPGA-based processors for an implementation-driven compiler construction course

This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the significant challenges in teaching using modern hardware platforms is the inordinate complexity of commonly used systems. To avoid this, many compiler courses target a less complex platform implemented via a simulator or a higher-level virtual or abstract hardware platform. To avoid the complexity of a modern superscalar multicore architecture and to improve the kinesthetic experience of students implementing the course compiler, we have provided a framework and runtime support for using an FPGA-based RISC CPU as the target for the compiler backend. Using this system allows students to leverage knowledge gained in earlier organization and architecture classes using the same system, while also providing a hands-on active learning component at the completion of the compiler implementation.

On the Inherent Resilience of Integer Operations

It is of great interest to correctly quantify corruption rates in computing systems. Masking effects of individual operations can complicate this effort by hiding faults. Beyond this, identification of fault-masking operations may be useful in designing resilient algorithms.

Using FPGAs as a reconfigurable teaching tool throughout CS systems curriculum

This paper describes the adaptation of several common computer science courses to include the use of FPGA-based systems for project and assignment work. One of the principal challenges in modern curriculum design is balancing between breadth and depth of course topics while simultaneously reinforcing the interconnections among topics in the field. To address these challenges, faculty are often forced to approximate real-world systems, sometimes at the expense of any hands-on experience. At Coastal Carolina, we have integrated FPGA systems first used in our hardware-based courses into several higher-level systems and applications courses. This allows us to leverage student familiarity with a hands-on, flexible hardware platform and also strengthens the relationships between different subfields within computer science. We discuss both the changes made to our curriculum and the effectiveness of our approach.

Using FPGA systems across the computer science curriculum (abstract only)

The field of computer science is continuously growing, requiring curriculum developers to make numerous tradeoffs between depth and breadth with every advance. Faculty must look for new ways to communicate more concepts within a fixed number of contact hours as well as employ techniques that underscore interrelated concepts over multiple courses. With this poster, we present the use of field-programmable gate arrays (FPGAs) as a flexible hardware system that may be modified to suit the needs of a wide variety of classes. While FPGA devices are a natural fit for teaching hardware concepts in organization and architecture classes, we feel that they can also be used in a variety of roles within a number of other courses. We describe our work integrating FPGA curriculum modules into several courses in the CS curriculum: organization and architecture, compiler construction, robotics, operating systems, security, and image processing. We believe that by using these devices in several courses, students gain greater familiarity with a hands-on, reconfigurable hardware platform and can leverage this experience throughout their coursework. This approach is consonant with recent trends that emphasize the importance of students being able to reason about the end-to-end operation of an entire system and helps strengthen the relationships between different subfields within computer science. We describe both the changes made to our curriculum and the effectiveness of our approach.

Introduction to using FPGAs in the computer science curriculum (abstract only)

One of the challenges in modern curriculum design is balancing between breadth and depth of topics while simultaneously reinforcing the interconnections among topics in the field. To address these challenges, faculty are often forced to approximate real-world systems, sometimes at the expense of any hands-on experience. We have integrated field-programming gate array (FPGA) systems first used in our hardware-based courses into several higher-level systems and applications courses. This allows us to leverage student familiarity with a hands-on, flexible hardware platform and also strengthen the relationships between different subfields within computer science. In this workshop, we present participants with guided hands-on activities for making use of FPGAs in common computer science courses such as digital logic design, computer organization and programming, and compiler construction. Laptop required.