D. Celi

230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications

This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.

A conventional double-polysilicon FSA-SEG Si/SiGe:C HBT reaching 400 GHz f MAX

This paper summarizes the work carried out to improve performances of a conventional double-polysilicon FSA-SEG SiGe:C HBT towards 400 GHz f<inf>MAX</inf>. The technological optimization strategy is discussed and electrical characteristics are presented. A record peak f<inf>MAX</inf> of 423 GHz (f<inf>T</inf> = 273 GHz) is demonstrated in SiGe:C HBT technology.

Impact of layout and technology parameters on the thermal resistance of SiGe:C HBTs

Calibrated 3-D numerical simulations supported by DC experimental data are employed to quantify the impact of the key layout and technology parameters on the thermal resistance of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) so as to define proper optimization criteria. The geometry parameters of a simple scalable model are optimized to describe the thermal resistance dependence upon emitter dimensions for the HBTs under analysis.

From measurement to intrinsic device characteristics: Test structures and parasitic determination

mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor. Original dummies are described and HF/DC measurements are presented and analyzed. Based on this limited set of structures a scalable de-embedding approach is described. To account for DC/HF parasitics, a sub-circuit is proposed for modeling purpose.

State-of-the-art and future perspectives in calibration and de-embedding techniques for characterization of advanced SiGe HBTs featuring sub-THz f T /f MAX

This paper presents an overview of RF calibration and pad de-embedding techniques, discusses limitations and demonstrates methods for accuracy improvement applicable for the characterization of advanced BiCMOS HBTs. The impact of the reference plane location is discussed. Numerous experiments with different device geometries showed that the in-situ (on-wafer) calibration yields the most accurate results. For a probe-tip calibration, a multiple-dummy de-embedding is crucial to improve measurement accuracy. A comparison with the compact model (HICUM V2.30) confirmed the findings.

Influence of probe tip calibration on measurement accuracy of small-signal parameters of advanced BiCMOS HBTs

This paper presents investigation results of the probe-tip calibration impact on the BiCMOS HBT small-signal parameter measurement accuracy. Popular calibration procedures were applied on the same data set and followed by the two-step de-embedding from the device dedicated Compete-Open and Complete-Short dummy elements. Experimental results showed that the observed difference in cold HBT parameters and parameters of passive devices was minimized by the de-embedding step. The ƒT and ƒMAX demonstrated higher sensitivity to the probe-tip calibration residual errors.

A new bipolar extraction tool for wide range of device behaviours

The recent development of BiCMOS and advanced bipolar and merged bipolar CMOS and DMOS technologies requires the enhancement of both models and parameter extraction strategies for the bipolar device. In order to take into account special behavior such as the base push-out effect or the nonideal base current, new features have been added to the classical SPICE BJT (bipolar junction transistor) model. A flexible software tool has been developed to allow the use of different parameter extraction schemes suitable for a wide range of device behaviors. Experimental validations have been performed in DC analysis. The RMS (root mean square) error on current gain is less than 2%.<<ETX>>

A Nodal Model Dedicated to Self-Heating and Thermal Coupling Simulations

Both reduction in device sizes and enhanced increase in current densities lead to concern about the impact of the self-heating effect on device electrical characteristics. Moreover, in power transistors applications, devices are connected in parallel, so thermal interaction between devices also has to be considered. In this paper, a nodal model is proposed in order to take into account temperature variation due to self-heating and thermal coupling. This model associated with the HICUM Level 2 version 2.21 compact model is validated thanks to measurements made on specific test structures.

Transit time parameter extraction for the HICUM bipolar compact model

This paper presents a extraction procedure for the transit time parameters of the HICUM bipolar compact model. The extraction routines use as input the measured small-signal current gain in the -20 dB/decade falloff region as a function of the collector current and the collector-emitter (or collector-base) voltage. All HICUM transit time parameters are extracted in a straightforward manner, no optimisation is necessary. Especially the critical current value ICK is determined in a self consistent way.

Extraction of the base-collector capacitance splitting along the base resistance using HF measurements [bipolar transistors]

This paper presents an efficient method to evaluate with accuracy the partitioning of the base-collector depletion capacitance through the base resistance by the way of the SPICE Gummel-Poon (SGP) model parameter X/sub CJC/. This parameter is directly extracted, without any optimization, from the real part of the high-frequency small-signal admittance Y/sub 12/ in common emitter configuration.