Sebastien Fregonese

A Comprehensive Graphene FET Model for Circuit Design

During the last years, graphene-based field-effect transistors (GFETs) have shown outstanding RF performance; therefore, they have attracted considerable attention from the electronic devices and circuits communities. At the same time, analytical models that predict the electrical characteristics of GFETs have evolved rapidly. These models, however, have a complexity level that can only be handled with the help of a circuit simulator. On the other hand, analog circuit designers require simple models that enable them to carry out fast hand calculations, i.e., to create circuits using small-signal hybrid - π models, calculate figures of merit, estimate gains, pole-zero positions, and so on. This paper presents a comprehensive GFET model that is simple enough for being used in hand calculations during circuit design and at the same time, it is accurate enough to capture the electrical characteristics of the devices in the operating regions of interest. Closed analytical expressions are provided for the drain current ID, small-signal transconductance gain gm, output resistance ro, and parasitic capacitances Cgs and Cgd. In addition, figures of merit, such as intrinsic voltage gain AV, transconductance efficiency gm/ID, and transit frequency fT are presented. The proposed model has been compared to a complete analytical model and also to measured data available in current literature. The results show that the proposed model follows closely to both the complete analytical model and the measured data; therefore, it can be successfully applied in the design of GFET analog circuits.

A computationally efficient physics-based compact bipolar transistor model for circuit Design-part I: model formulation

A compact bipolar transistor model is presented that combines the simplicity of the SPICE Gummel-Poon model (SGPM) with some major features of HICUM. The new model, called HICUM/L0, is more physics-based and accurate than the SGPM and at the same time, from a computational point of view, suitable for simulating large circuits. The new model has been implemented in Verilog-A and, as compiled code, in various commercial circuit simulators. In Part I, the fundamental model formulation is presented along with a derivation of the most important equations. Experimental results are shown in Part II.

A Scalable Electrothermal Model for Transient Self-Heating Effects in Trench-Isolated SiGe HBTs

This paper demonstrates a scalable electrothermal model for transient self-heating effects in trench-isolated SiGe heterojunction bipolar transistors (HBTs). The scalability of the thermal model has been investigated by considering pyramidal heat diffusion approximation between the heat source and the thermal ground. Three-dimensional thermal TCAD simulations have been carried out to obtain transient variations of the junction temperature and to extract the thermal impedance in the frequency domain. A recursive thermal network with scalable model parameters has been developed and added at the temperature node of the HBT compact model HiCuM. This network has been verified through numerical simulations and by low-frequency s-parameter measurements and found to be in excellent agreement for various device geometries.

Thermal Impedance Modeling of Si–Ge HBTs From Low-Frequency Small-Signal Measurements

In this letter, the thermal impedance of SiGe heterojunction bipolar transistors has been characterized using low-frequency small-signal measurements. Theoretical works for thermal impedance modeling using different electrothermal networks, developed until date, have been verified with our experimental results. We report for the first time the experimental verification of the electrothermal model for thermal impedance developed by Mnif using a nodal and recursive network. A generalized expression of the frequency-domain thermal impedance has been selected for electrical compact transistor model (HiCuM) improvement, parameter extraction, and electrothermal network verification.

Electrical Behavior and Technology Optimization of Si/SiGeC HBTs on Thin-Film SOI

A growing interest has been focused on silicon on insulator (SOI) technologies over the past years. Yet, few studies were carried out regarding the integration of vertical SiGe heterojunction bipolar transistors (HBTs) using such substrates. This paper deals both with the integration of a SiGeC HBT on thin-film CMOS-compatible SOI, and a comprehensive study of its electrical behavior based on physical simulation and electrical characterization. Various aspects of the optimization of device performances are described, considering process or layout improvements.

Characterization and Modeling of Graphene Transistor Low-Frequency Noise

This brief presents low-frequency noise measurements on a graphene field-effect transistor with graphene layer decomposed from SiC substrate. The measurements indicate the predominance of flicker noise in the current noise source measured between drain and source with quadratic dependence with a drain current. The noise level is inversely proportional to the channel area indicating the location of the main noise source to be in graphene layer. From these measurements, the main noise sources, including the main flicker noise and the Johnson noise contributions, have been introduced in a compact model. This compact model has been built using dc characterization results. Finally, the noise compact model has been validated through comparison to noise measurement.

Modeling of Strained CMOS on Disposable SiGe Dots: Strain Impacts on Devices' Electrical Characteristics

We proposed a new nonplanar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress, both from the underlaying SiGe 3-D islands and from the stressed capping layers. We show that more than 80% and 50% higher mobilities of holes and electrons, respectively, can be obtained, as indicated by 3-D simulations performed throughout the entire fabrication process. Significant improvements in drive currents, transit frequencies, and the short channel effects are demonstrated using 2-D device simulation.

Compact Model of a Dual Gate CNTFET: Description and Circuit Application

We present a physical compact model of a dual gate carbon nanotube field effect transistor (DG CNTFET). To obtain an accurate and predictive model, the expression of the drain current is based on the description of the local channel potentials as well as the injected charge. The comparison between the simulation results and experiments highlights the influence of the parasitic Schottky barrier at high injection level. Hence, assuming a higher DG-CNTFET technology maturity, this predictive model allows to evaluate the performance of logic circuits in terms of reconfigurable architecture.

A scalable model for temperature dependent thermal resistance of SiGe HBTs

This paper presents a geometry scalable approach for temperature dependent thermal resistance (RTH) calculations in trench-isolated SiGe heterojunction bipolar transistors (HBTs). The model is able to predict the RTH at any temperature and power dissipation (Pdiss). The temperature dependency is obtained by discretizing the heat flow region into n-number of elementary slices depending on the temperature gradient. RTHs of each slice are calculated using temperature dependent thermal conductivity. The results are compared to 3D thermal TCAD simulations for a wide range of ambient temperature (Tamb), Pdiss and device dimensions. Finally, the scalability is validated through measurements of several transistor geometries as well as two different technologies and found to be in good agreement.

A charge approach for a compact model of Dual Gate CNTFET

We present a physical approach to model the dual gate CNTFET. In this transistor, whose type (N or P) depends on the back gate bias, the charge of each region (source and drain accesses and inner part) remains an essential quantity to evaluate the channel potential and thus the drain current. The charges are calculated (i) considering 0 or 1 carrier transmission probability and (ii) assuming that the carrier energy is not affected by back-scattering mechanisms to obtain a physical compact description. Using this compact model, typical electrical characteristics of such transistor are presented.