D.D. Tang

Spin-valve RAM cell

This paper presents the design and the characteristics of a nonvolatile memory cell using giant magneto-resistance effects. Unlike other magnetic memory cells, the present cell design exploits the full /spl Delta/R of the spin valve material. A dc voltage difference between the two cell states of 30 mV range has been realized on a cell stripe only 6-microns long, making it compatible with the high-speed sensing schemes presently employed in silicon RAMs. The cell switches states in sub-nanoseconds. Its performance/density is close to that of the static RAM cell.

Heavy doping effects in p-n-p bipolar transistors

This paper presents the heavy doping effects on the injection current characteristics in p-n-p transistors with a heavily doped but thin base region. The results of the present study indicate that 1) at room temperature the hole current injected into heavily doped base is insensitive to the impurity compensation effect, 2) a linear relationship between the base sheet resistance and the collector-current density is observed when the base doping density is under 1 × 1019cm-3. This relationship becomes supralinear as the doping density further increases. As a result, useful current gain exists in thin base transistors even when the base doping is greater than 1 × 1019cm-3. From the collector-current-base sheet-resistance relationship and the base doping profile, the effective intrinsic carrier density as a function of the doping density is evaluated and found to increase 8.7 times over that of pure silicon, when the average doping density is 5 × 1019cm-3(maximum doping density 1 × 1020cm-3). 3) The collector current and the current gain of the transistors become less sensitive to the temperature as the base doping density increases. We had observed a current gain up to 30 at 77 K for transistors with the maximum base doping density in the 1018cm-3range. The transistors with lower base doping suffer much more degradation in current gain when the temperature is lowered to 77 K.

A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology

Key design parameters of 64 Mb STT-MRAM at 90-nm technology node are discussed. A design point was developed with adequate TMR for fast read operation, enough energy barrier for data retention and against read disturbs, a write voltage satisfying the long term reliability against dielectric breakdown and a write bit error rate below 10-9. A direct experimental method was developed to determine the data retention lifetime that avoids the discrepancy in the energy barrier values obtained with spin current- and field-driven switching measurements. Other parameters detrimental to write margins such as backhopping and the existence of a low breakdown population are discussed. At low bit-error regime, new phenomenon emerges, suggestive of a bifurcation of switching modes. The dependence of the bifurcated switching threshold on write pulse width, operating temperature, junction dimensions and external field were studied. These show bifurcated switching to be strongly influenced by thermal fluctuation related to the spatially inhomogeneous free layer magnetization. An external field along easy axis direction assisting switching was shown to be effective for significantly reducing the percentage of MTJs showing bifurcated switching.

On the low-temperature static and dynamic properties of high-performance silicon bipolar transistors

In a study performed over the temperature range of 400 to 77 K, Si bipolar transistors were found to have near-ideal characteristics at low temperatures with beta as high as 80 at 77 K. Detailed calculations indicate that the conventional theory of the temperature dependence of beta does not match the data. The discrepancy can be removed if it is assumed that a phenomenological thermal barrier to hole injection is present. Emitter-coupled logic (ECL) ring oscillators are functional at 85 K with no degradation in speed until about 165 K when compared to 358 K (85 degrees C). Calculations using a delay figure of merit indicate that f/sub T/, R/sub b/, and C/sub c/ are the delay components most affected by low-temperature operation. The feasibility of reduced logic swing operation of bipolar circuits at low temperatures is examined. It is found that successful ECL circuit operation at reduced logic swings is possible provided emitter resistance is kept small and can be used to enhance low-temperature power-delay performance. These data suggest that conventionally designed high-performance bipolar devices are suitable for the low-temperature environment. >

Inherent and stress-induced leakage in heavily doped silicon junctions

Inherent leakage currents and leakage induced with reverse-bias stress are investigated in heavily doped emitter-base junctions of polysilicon self-aligned bipolar transistors and similar diodes. Inherent in the devices is a reverse leakage component found to have a perimeter trap-assisted tunneling component characteristic of the Si-SiO/sub 2/ surface and evident at doping insufficient for significant band-to-band tunneling. The band-to-band phonon-assisted tunneling and avalanche leakage components are also identified. Introducing surface states through reverse-bias stress induces a Pool-Frenkel electric field enhanced generation/recombination surface leakage component. The induced and trap-assisted tunneling components are distinct. The induced component is found to saturate as available states, dependent on the peak electric field, are exhausted. Trapped charge accumulation after extensive stressing affects the electric field along the surface reducing the induced and trap-assisted tunneling leakage components. >

A novel high-performance lateral bipolar on SOI

A novel lateral bipolar structure on SOI (silicon-on-insulator) is described. This device has a thin double-diffused base and a narrow emitter width, determined by the SOI thickness. It has minimal parasitic junction capacitance, as well as minimal emitter and collector resistances. Excellent device characteristics and an f/sub T/ of about 20 GHz were demonstrated.<<ETX>>

A submicrometer high-performance bipolar technology

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated.<<ETX>>

Design considerations of high-performance narrow-emitter bipolar transistors

The control of the lateral diffusion of the extrinsic base is a key issue in the downscaling of high-speed bipolar transistors for achieving the lowest base resistance without altering the shallow impurity profile of the intrinsic region. This letter will present the effects of lateral encroachment of the extrinsic-base dopant on the characteristics of transistors with submicrometer emitter stripe width, measurement of the amount of encroachment, and its relationship to the vertical profile.

1.25 /spl mu/m Deep-Groove-Isolated Self-Aligned Bipolar Circuits

This paper concerns the design and characteristics of the high-performance bipolar switching devices and circuits for digital applications at lithographic dimensions of about 1 /spl mu/m. The impurity profile of the transistors is optimized for speed while maintaining sufficient current gain and punchthrough voltage. The circuits were fabricated on epitaxial wafers of a 0.5 /spl mu/m flat zone in an advanced bipolar technology featuring self-aligned polysilicon base and emitter contacts, deep-groove device isolation, and electron beam lithography. The experimental results show that n-p-n transistors exhibit a current gain greater than 40 at current densities as high as 1.3 mA//spl mu/m/sup 2/. As a result of reduced line width and polysilicon contacts, the current gain of Iateral epi-base p-n-p transistors is greater than 20 at low-current levels and remains greater than 1 at a current density as high as 0.12 mA//spl mu/m emitter edge. ECL (FI = FO = 1) circuits show a gate delay as low as 114 pS at a power dissipation of 4.9 mW. High-density I/sup 2/L/MTL circuits (average FI = 2, FO = 2.5, C/sub w/ = 90 fF) show delay of 0.91 ns at 0.17 mW. These results demonstrate that the present bipolar technology provides not only high-speed circuits, but also circuits for VLSI applications with density comparable to MOSFET.

50-GHz self-aligned silicon bipolar transistors with ion-implanted base profiles

Silicon bipolar transistors having cutoff frequencies from 40 to 50 GHz have been fabricated in a double -polysilicon self-aligned structure using a process which relies on ion implantation for the intrinsic base formation. The devices have nearly ideal DC characteristics, with breakdown voltages adequate for most digital applications. The results demonstrate that the performance limits of conventional implanted technologies are significantly higher than previously thought.<<ETX>>