Chao-Hsiung Wang

Novel Strained-Si Substrate Technology for Transistor Performance Enhancement

Strained-Si channel transistors offer significant perforrnance enhancement. However, most designs based on bulk-Si subsfrates utilize thick SiGe buffer layers or complex multi-layer structures for the intoduction of tensile strain in the Si channel and might not be easily or economically integrated into a conventional cMos process t1]. Various methods to irnplement sfiained-Si subsfrates based on silicon-on-insulator (SOf wafers have also been demonstated [2]-[3], but they suffer from an inherent high cost and process corrplexity. In this paper, we present a new, inexpensive, and manufactuable strained-Si substrate technology based on bulk-Si subsfiate, and demonstrate significant enhancement in fransistor perfonnance.