D. Doughty

A VXIbus based trigger for the CLAS detector at CEBAF

A VXIbus-based first-level triggering system for the CLAS detector at CEBAF (Continuous Electron Beam Accelerator Facility, Newport News, VA) has been designed and prototyped. It uses pipelining and a triple memory lookup to produce a deadtimeless trigger decision with an average latency of 110 ns and a jitter of 20 ns. The VXIbus Extended Start/Stop triggering protocols allow subnanosecond time synchronization. >

A 250 MHz Level 1 Trigger and Distribution System for the GlueX experiment

The GlueX detector now under construction at Jefferson Lab will search for exotic mesons though photoproduction (10^8 tagged photons per second) on a liquid hydrogen target. A Level 1 hardware trigger design is being developed to reduce total electromagnetic (≪ 200 MHz) and hadronic (≫ 350 kHz) rates to less than 200 kHz. This trigger is deadtimeless and operates on a global synchronized 250 MHz clock. The core of the trigger design is based on a custom pipelined flash ADC board that uses a VXS backplane to collect samples from all ADCs in a VME crate. A custom switch-slot board called a Crate Trigger Processor (CTP) processes this data and passes the crate level data via a multi-lane fiber optic link to the Global Trigger Processing Crate (also VXS). Within this crate detector sub-system processor (SSP) boards can accept all individual crate links. The subsystem data are processed and finally passed to global trigger boards (GTP) where the final L1 decision is made. We present details of the trigger design and report some performance results on current prototype systems

The use of content addressable memories in the level 2 trigger for the CLAS detector at CEBAF

The LEVEL 2 trigger in the CLAS detector will find tracks and associate a momentum and angle with each track within 2 ps after the event. This is done through a hierarchical track finding design in which track segments ae found in each dnft chamber axial superlayer. An m y of 384 custom content addressable (or associative) memories (CAMS) uses independent subfield matchng to link these track segments into roads. The track parameters corresponding to each found road are then looked up in a separate memory. We present the overall architecture of the LEVEL 2 trigger, the details of how the CAM chip links tracks segments to find roads, and report on the performance of our prototype CAM chips.

Asynchronous inputs and flip-flop metastability in the CLAS trigger at CEBAF

The impact of flip-flop metastability on the pipelined trigger of the CEBAF Large Acceptance Spectrometer (CLAS) detector at the Continuous Electron Beam Accelerator Facility (CEBAF) is studied. It is found that the newest emitter-coupled logic (ECL) flip-flops (ECLinPS) are much faster than older families (10 H) at resolving the metastable condition. This will allow their use in systems with asynchronous inputs without an extra stage of synchronizing flip-flops. >

A content addressable memory for use in CEBAF's CLAS detector level 2 triggering system

A collaboration of researchers from CEBAF, CNU and NASA is designing a 256/spl times/32 specialized Content Addressable Memory (CAM) for the level 2 triggering system in CEBAFs CLAS detector. These integrated circuits will find tracks and the momentum and angle of each track within 2 microseconds of an event. The custom CAM can operate as conventional memory, performing read and write operations, and can additionally perform independent byte compare operations across all words simultaneously. It is this compare feature which makes these CAMs attractive for identifying tracks passing through drift chambers by linking together segment number triplets within the CAM. Simulations have indicated that less than 16 k triplets need to be stored for each sector of the detector. This implies the level 2 triggering can be performed with 64 CAM chips per sector, or 384 total. Each data channel into a sector CAM array is buffered in a FIFO and is designed to handle aggregate data rates up to 750 Mbs for three channels (one channel/superlayer). The architecture of the level 2 trigger and details of the CAM chip design are discussed along with a performance report on our prototype CAMs.