D.E. Van den Bout

Graph partitioning using annealed neural networks

A new algorithm, called mean field annealing (MFA), is applied to the graph partitioning problem. The MFA algorithm combines characteristics of the simulated annealing algorithm and the Hopfield neural network. MFA exhibits the rapid convergence of the neural network while preserving the solution quality afforded by stochastic simulated annealing (SSA). The MFA algorithm is developed in the context of the graph partitioning problem. The rate of convergence of MFA on graph bipartitioning problems is as much as 50 times that of SSA, yet does not degrade the quality of the final solution. The temperature behavior of MFA during bipartitioning is analyzed and shown to have an impact on the tuning of neural networks for improved performance. Also presented is a new modification to MFA that supports partitioning of random or structured graphs into three or more bins-a problem that has previously shown resistance to solution by neural networks.<<ETX>>

A digital architecture employing stochasticism for the simulation of Hopfield neural nets

A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed ( approximately=N*10/sup 8/ connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing. >

AnyBoard: an FPGA-based, reconfigurable system

AnyBoard, a low-cost, field programmable gate array (FPGA)-based, reconfigurable rapid-prototyping system is described. The system hardware organization and software tools that help users automatically map designs to the FPGAs and manage the design process are discussed. The implementation of a pattern generator design is presented to illustrate the systems effectiveness.<<ETX>>

The TInMANN VLSI chip

A massively parallel, all-digital, stochastic architecture-TInMANN-that acts as a Kohonen self-organizing feature map is described. A VLSI design is shown for a TInMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be configured to build networks of arbitrary size. The neuron operates at a speed of 15 MHz, making it capable of processing 195000 three-dimensional training examples per second. Three man-months were required to synthesize the neuron and its associated level-sensitive scan logic using the OASIS silicon compiler. The ease of synthesis allowed many performance trade-offs to be examined, while the automatic testability features of the compiler helped the designers achieve 100% fault coverage of the chip. These factors served served to create a fast, dense, and reliable neural chip.

The AnyBoard: programming and enhancements

The programming of the AnyBoard is demonstrated by the design of a simple direction finder. The operations needed to enter, simulate, store, map, and debug a design are discussed. The length of time needed to accomplish each of these operations is used to justify some proposed enhancements to the AnyBoard Rapid-Prototyping Environment. >The programming of the AnyBoard is demonstrated by the design of a simple direction finder. The operations needed to enter, simulate, store, map, and debug a design are discussed. The length of time needed to accomplish each of these operations is used to justify some proposed enhancements to the AnyBoard Rapid-Prototyping Environment.<<ETX>>

The Anyboard: a rapid-prototyping system for use in teaching digital circuit design

A rapid prototyping system for teaching digital design is described. The system uses electronically-reconfigurable field programmable gate arrays (FPGAs) to implement a specific logic design without requiring any physical changes to the prototyping system. The user specifies designs using a text based description language. The prototyping system partitions the input logic among the available FPGA resources while observing constraints on gate density and chip I/O. The combinational logic blocks (CLBs) in each individual FPGA are then placed and the interconnections are routed. Once programmed, the system can be exercised using a pattern generator and logic analyzer. The Anyboard system reduces the time required to implement a design and avoids some of the problems associated with the use of wire-wrap or prototyping board implementations.<<ETX>>

The VLSI implementation of STONN

A 100000-transistor digital CMOS Hopfield neural network is presented, and its performance is discussed. STONN uses space efficient stochastic logic and bitwise pipelining to achieve massive parallelism and high operational speeds. The architecture produces solutions to optimization problems with a quality equivalent to that of solutions produced by analog networks and nearly as good as those found using simulated annealing. The massively parallel nature of STONN increases its speed of convergence by orders of magnitude over uniprocessor implementations. The completely digital STONN design provides dynamically reprogrammable parameters and a practical system implementation which can be expanded using several identical chips

Optimization of transmitter and receiver filters for digital communication systems using mean field annealing

A technique for finding transmitter and receiver filters for a wide class of digital communication systems which minimize the bit-error rate (BER) is presented. The technique uses Monte Carlo simulation to estimate the BER and mean field annealing (MFA) to optimize the pulse shapes. Modeling of the link can be as complex as simulation will allow, while MFA is resistant to the statistical variation in the BER estimate from the simulation. Initially, the MFA technique was applied to a binary symmetric channel in a nonsimulation environment, and an approximate analysis of the behavior of MFA for this problem was performed. In a more complex example, MFA was coupled with Monte Carlo simulation techniques to find near-optimal transmit and receive filters for a satellite communications link, taking 6 CPU hours on a DECstation 3100. The BER of the link was found to be as much as three orders of magnitude lower when using the MFA-constructed optimal filters than when using filters from other comparison results. For this example, the pulse shapes obtained using MFA exhibit a low BER even as the parameter controlling the nonlinearity of the satellite-link model is varied over a wide range, thus showing the solution is robust. >

Encoding logical constraints into neural network cost functions

The authors introduce the use of logical consequences in determining cost functions for neural networks which solve optimization or constraint-satisfaction problems. This technique estimates the changes required in the remaining neuron outputs in order to maintain a valid solution when a selected neuron is forced on or off. From this estimate, an estimate can be made of the cost change due to the change in the selected neuron. The set of estimated costs for all the neurons is then used to update their respective outputs. Applying logical consequences in some problems eliminates the need to use penalty functions to transform constrained problems into unconstrained problems suitable for solution by neural nets. The neural nets derived with this technique nearly always produced valid solutions to the traveling salesman problem, and the solutions were only 5% above the best solutions found using simulated annealing. Graph bipartitioning was also performed, but the percentage of balanced solutions fell into the 70% to 90% range due to a violation of one of the implicit assumptions in the model

The 1993 AnyBoard rapid-prototyping environment

The programming of the AnyBoard is demonstrated by the design of a digital oscilloscope. The operations needed to enter, simulate, store, map, and debug a design are designed. The length of time needed to accomplish each of these operations is used to justify some proposed enhancements to the AnyBoard rapid-prototyping environment.<<ETX>>