Thomas K. Miller

Graph partitioning using annealed neural networks

A new algorithm, called mean field annealing (MFA), is applied to the graph partitioning problem. The MFA algorithm combines characteristics of the simulated annealing algorithm and the Hopfield neural network. MFA exhibits the rapid convergence of the neural network while preserving the solution quality afforded by stochastic simulated annealing (SSA). The MFA algorithm is developed in the context of the graph partitioning problem. The rate of convergence of MFA on graph bipartitioning problems is as much as 50 times that of SSA, yet does not degrade the quality of the final solution. The temperature behavior of MFA during bipartitioning is analyzed and shown to have an impact on the tuning of neural networks for improved performance. Also presented is a new modification to MFA that supports partitioning of random or structured graphs into three or more bins-a problem that has previously shown resistance to solution by neural networks.<<ETX>>

A digital architecture employing stochasticism for the simulation of Hopfield neural nets

A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed ( approximately=N*10/sup 8/ connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing. >

A system architecture for intelligent implantable biotelemetry instruments

A system architecture for intelligent implantable biotelemetry instruments is presented. The system consists of a modular chip set interconnected by a synchronous serial bus. A user-programmable microprocessor controls all functions, including data acquisition, actuator control and telemetry. Data acquisition is performed by an eight-channel conditioning chip with programmable gain, bandwidth, and sampling rates. An advanced telemetry unit allows bidirectional communication of both data and commands, while providing an error-detection scheme to ensure integrity.<<ETX>>

A microprocessor-based implantable telemetry system

The design methodology of an intelligent system for implantable biotelemetry instruments based on a modular set of CMOS chips connected by a specialized serial bus is described. General system requirements are discussed, and an overview of the system is given. The design of the serial buses, custom microprocessor, bidirectional telemetry chip, and sensor interface is described. Clock requirements are considered.<<ETX>>

An SIMD Multiprocessor Ring Architecture for the LMS Adaptive Algorithm

A new architecture for a single instruction stream, multiple data stream (SIMD) implementation of the LMS adaptive algorithm is investigated. This is denoted as a ring architecture, due to its physical configuration, and it effectively solves the latency problem often associated with prediction error feedback in adaptive filters. The multiprocessor ring efficiently updates the filter input vector by operating as a pipeline structure, while behaving as a parallel structure in computing the filter output and applying the weight adaptation algorithm. Last, individual processor timing and capacity considerations are examined.

Standard Errors on Respiratory Mechanical Parameters Obtained by Forced Random Excitation

Equations describing the standard errors of forced random impedance data and derived parameters in terms of various data collection and data processing factors were developed and verified. The equation indicate that to obtain reliable estimates: 1) 16 ensembles are adequate when coherence is greater than 0.9, and that 32 ensembles are adequate when the coherence is between 0.8 and 0.9; 2) the impedance of the bias tube should be at least two times the impedance of the respiratory system in the bandwidth of the applied noise; and 3) the spectrum should include at least 20 frequencies with at least 2 and preferably more below 10 Hz. Fortunately, all of these constraints can be satisfied with most subjects. This analysis also provides a basis for using weighted regression in estimating resistance, inertance, and compliance parameters, and for separating observed parameter variability into methodological and physiological components.

Engineering and Innovation: An Immersive Start-up Experience

The paper mentions that the Engineering Entrepreneurs Program has been helping engineering students become entrepreneurs. What began as informal student meetings has grown to a three-course sequence with graduates who have pioneered successful companies. Assessments show a positive correlation between program participation and entrepreneurial action.

Faculty teaching practices and perceptions of institutional attitudes toward teaching at eight engineering schools

All engineering faculty members in the eight universities that comprise the SUCCEED Coalition were surveyed about their use of a variety of instructional methods and their perceptions about attitudes toward teaching on their campuses. The results provide a unique snapshot of engineering education at a transitional moment in its history. The same survey will be administered two years and four years from now. The results should provide an indication of the degree to which the SUCCEED faculty development program is meeting its objectives, which are to promote facility adoption of proven instructional methods and materials and to improve institutional support for effective teaching.

System-level specification of instruction sets

System-level design requires some sort of specification for a system at the level of abstraction of the system. When the system (or sub-system) is a processor, the appropriate level of abstraction is the instruction set. However, there are no good approaches for describing processors at this level. Nevertheless, this type of specification has a number of benefits: it is more concise (and thus less error-prone) than more general alternatives; it can be re-used in later re-implementations; and it provides support for software codesign through compiler-generators (which rely on higher-level abstractions than other techniques provide). Therefore, we have developed a methodology and an embodying language for specifying processors at the instruction set level.<<ETX>>

Rapid Prototyping for Neural Networks

A massively parallel, all-digital, stochastic architecture — TInMANN — is described which performs competitive and Kohonen types of learning at rates as high as 145,000 training examples per second. TInMANN is composed of very simple neurons and is very amenable to VLSI implementation, but rapid advances in IC technology and neural network theory reduce the rewards of such an endeavor. As an alternative, we discuss the rapid-prototyping of a bit-serial version of TInMANN using commercially available logic cell arrays and RAMs.