D. Eirug Davies

POST ANNEALING CONDUCTANCE BEHAVIOR OF IMPLANTED LAYERS IN SILICON

Isochronal annealing studies have been conducted on implanted boron and phosphorus layers in silicon. It is shown that the sheet conductance rise on annealing is dependent on the temperature at which the silicon is maintained during implantation. From the standpoint of conductance, low‐temperature implanting is to be favored.

Compensation from implantation in GaAs

Non‐dopant ions have been implanted at low doses ([inverted lazy s] 1010 cm−2) into GaAs to determine the extent of carrier removal and to pin‐point annealing stages for carrier recovery. A removal rate of around 200 carriers per ion is found for such lighter ions as B+, N+, and F+. At the 1‐MeV energy used, compensating damage extends along the ion track right from the GaAs wafer surface. Partial recovery of the carriers as well as mobility occurs at the well‐known 225 °C electron damage annealing stage. A further annealing stage is found at [inverted lazy s] 525 °C.

Pulse electron annealing of ion‐implanted InP

Pulsed electron beam annealing has been used to activate high‐dose silicon implants in InP. Peak concentrations ≳ 1019 cm−3 are obtained without any appreciable carrier freezeout on cooling to 78 °K. Such activation is comparable to that obtained on thermal annealing and is seen on samples implanted at both room temperature (amorphous) and 200 °C. In common with the behavior reported for GaAs, the mobility is similarly curtailed below thermally annealing values. Though the initial polished appearance is generally retained, unusual thermal oxidation and anodization properties suggest the possibility of surface phosphorous loss.

Improved electrical mobilities from implanting InP at elevated temperatures

InP has been implanted with silicon to investigate the effect of implantation temperature on the postannealed electrical mobility. A significant improvement, by a factor of ∼2, occurs on implanting at 200 °C rather than at room temperature. Dislocations found after the room‐temperature but not the 200 °C implants may account for the mobility differences.

Enhanced activation of Zn‐implanted GaAs

Limitations on high level doping have been investigated for implanted Zn in GaAs. Fast diffusive redistribution during the annealing of heavy dose Zn implants generally leads to broader doped layers of lesser concentrations. Though such a redistribution can be prevented by short duration annealing of ∼1 s, this alone is not sufficient to increase the peak concentration. Significantly better activation can be obtained if an excess of As is also provided. It is found that coimplanting As with Zn in addition to short duration annealing provides layers with peak doping concentrations increased to levels approaching 1020 cm−3. Doping enhancement related to encapsulation and the outdiffusion of Ga into SiO2 has also been observed.

Pulse annealing deficiencies in GaAs

Heavily doped epitaxial GaAs has been subjected to pulse electron beam annealing. Differential Hall measurements indicate that the annealing causes a reduction in the majority carrier density and severely curtails the carrier mobility. The thickness of such affected material is increased with any subsequent heat treatment. These results suggest that compensating defects are produced by the pulse annealing and that these migrate inwards from the surface during thermal annealing. It is considered that such defects account for the general failure to activate low‐dose implants, the loss of high‐dose activation with moderate heat treatment, and the invariably poor mobilities within pulse‐annealed implanted layers.

InP surface conducting films from electron‐pulse annealing

Heavily conducting layers have been observed in InP subjected to pulse electron beam annealing. No implantation is involved and sheet resistivities of ∼10 Ω/⧠ are typically obtained. The conduction is confined to within ∼500 A of the surface and is annealable thermally ∼400 °C. Indicated concentrations are ≳1021 cm−3. Both electron microscopy and Rutherford backscattering show that electron beam annealing leads to a phosphorus loss at the surface. It is presumed that the observed conduction can be attributed to some defect associated with phosphorus loss.

RESIDUAL ELECTRICALLY ACTIVE DEFECTS AFTER LATTICE REORDERING IN ION‐IMPLANTED SILICON

Thermally stimulated current measurements have been conducted on low‐dose carbon‐implanted silicon. After annealing for lattice reordering, five defect levels are found still present and of energies ranging from 0.27 to 0.40 eV. Since they all show similar annealing to above 500°C, they reveal a major annealing stage in low‐dose ion‐implanted silicon that occurs at considerably higher temperatures than what is generally ascribed to lattice reordering.

Compensation from implantation damage in InP

Compensation arising from ion damage has been investigated in InP. It is found that ≳10 times the irradiation that produces resistive layers in GaAs is required to similarly compensate InP. The damage anneals in two stages indicating that two distinct defects contribute to the carrier removal process. Partial annealing at ∼400 °C rather than at 500 °C as in GaAs is suggested as a means of producing low‐absorption highly resistive layers. From compensation considerations annealing to at least 550 °C will be required for dopant implantations if effective electrical utilization is to be achieved.

MINORITY CARRIER LIFETIME IN ION‐IMPLANTED AND ANNEALED SILICON

Results are presented of an investigation to determine whether minority carrier lifetime within ion‐implanted layers can be restored to preirradiation levels by annealing. Reverse‐recovery measurements were conducted on diffused diodes damaged on the low‐doped side by light doses of carbon. The results show that practically complete recovery can be obtained, but annealing beyond the 400°C range associated with light‐dose lattice reordering to as high as 600–650°C is required.