J. P. Lorenzo

Implantation and PH 3 Ambient Annealing of InP

layers have been annealed using the same phosphorus ambient conditions as would be encountered during the materials vapor phase epitaxial growth. Implanted layers so annealed exhibit sheet carrier concentrations up to with the n‐type silicon ion and approximately 1014 cm−2 with the p‐type Mg ion. No indication of outdiffusion is seen on layers that have been profiled. Though the annealing was undertaken in an epitaxial reactor, it is envisioned that a much simplified system would also suffice. The present approach provides an alternative to the more customary dielectric encapsulation whose effectiveness is often impaired by deposition variations.

N-type doping of indium phosphide by implantation

Implantation has been investigated as a means of producing n-type doped layers in indium phosphide. It is found that sulfur is best implanted at elevated temperatures and sheet carrier concentrations of ⪞1014cm−2 are readily obtained on annealing at ⪞650°C. Satisfactory layers of comparable doping result on implanting silicon at room temperature but higher annealing, ⪞750°C, is required. Peak carrier concentrations of ⪞1019cm−3f, significantly better than in similarly implanted GaAs, are attainable in indium phosphide.

Pulse electron annealing of ion‐implanted InP

Pulsed electron beam annealing has been used to activate high‐dose silicon implants in InP. Peak concentrations ≳ 1019 cm−3 are obtained without any appreciable carrier freezeout on cooling to 78 °K. Such activation is comparable to that obtained on thermal annealing and is seen on samples implanted at both room temperature (amorphous) and 200 °C. In common with the behavior reported for GaAs, the mobility is similarly curtailed below thermally annealing values. Though the initial polished appearance is generally retained, unusual thermal oxidation and anodization properties suggest the possibility of surface phosphorous loss.

Improved electrical mobilities from implanting InP at elevated temperatures

InP has been implanted with silicon to investigate the effect of implantation temperature on the postannealed electrical mobility. A significant improvement, by a factor of ∼2, occurs on implanting at 200 °C rather than at room temperature. Dislocations found after the room‐temperature but not the 200 °C implants may account for the mobility differences.

Pulse annealing deficiencies in GaAs

Heavily doped epitaxial GaAs has been subjected to pulse electron beam annealing. Differential Hall measurements indicate that the annealing causes a reduction in the majority carrier density and severely curtails the carrier mobility. The thickness of such affected material is increased with any subsequent heat treatment. These results suggest that compensating defects are produced by the pulse annealing and that these migrate inwards from the surface during thermal annealing. It is considered that such defects account for the general failure to activate low‐dose implants, the loss of high‐dose activation with moderate heat treatment, and the invariably poor mobilities within pulse‐annealed implanted layers.

Electron Microscope Study of Annealed SiH2 + Implanted InP

Transmission electron microscopy was used to characterize structural defects in annealed implanted both at room temperature and at 200°C with at 150 keV. During implantation at room temperature an amorphous layer was formed to a depth of ~1850A, whereas no such layer was formed on the specimen implanted at 200°C. Upon recrystallization of the amorphous layer at 650°C or higher shear dislocations were observed as well as loop structures up to 2000A in diameter on {111} and {110} planes within that region. Smaller, interstitial loops were present on {110} planes throughout the implanted region. The specimens implanted at 200°C did not go through a recrystallization stage. Therefore, no shear dislocations were formed in this case. However, these specimens when annealed to 650°C or higher contained loops under 100A in size. The structural differences observed between the room temperature and 200°C implants may account for the higher carrier mobility measured for the 200°C implant.

InP surface conducting films from electron‐pulse annealing

Heavily conducting layers have been observed in InP subjected to pulse electron beam annealing. No implantation is involved and sheet resistivities of ∼10 Ω/⧠ are typically obtained. The conduction is confined to within ∼500 A of the surface and is annealable thermally ∼400 °C. Indicated concentrations are ≳1021 cm−3. Both electron microscopy and Rutherford backscattering show that electron beam annealing leads to a phosphorus loss at the surface. It is presumed that the observed conduction can be attributed to some defect associated with phosphorus loss.

Compensation from implantation damage in InP

Compensation arising from ion damage has been investigated in InP. It is found that ≳10 times the irradiation that produces resistive layers in GaAs is required to similarly compensate InP. The damage anneals in two stages indicating that two distinct defects contribute to the carrier removal process. Partial annealing at ∼400 °C rather than at 500 °C as in GaAs is suggested as a means of producing low‐absorption highly resistive layers. From compensation considerations annealing to at least 550 °C will be required for dopant implantations if effective electrical utilization is to be achieved.

High‐purity InP grown on Si by organometallic vapor phase epitaxy

We have grown by organometallic vapor phase epitaxy high‐purity InP on Si substrates using a GaAs intermediate layer. The InP layers exhibit residual electron concentration as low as 5×1014 cm−3 and electron mobilities as high as 4000 and 25 000 cm2/V s at 300 and 77 K, respectively. The achieved InP quality is dependent on the GaAs intermediate layer thickness. These excellent electrical properties are due to high crystal qualities as evidenced by x‐ray rocking curve half width as low as 215 arcsec and defect densities on the order 108 cm−2. p/n junctions, with ideality factors as low as 1.6 and low leakage currents, confirm the device quality of this material.

Electron‐pulsed diffusion of Se in GaAs

n+ regions with concentrations exceeding 1019 cm−3 have been formed in GaAs by pulse diffusion with an electron beam. The diffusion source is a deposited As2Se3 film which is removed by the pulse without unduly affecting the initial polished appearance of the GaAs. The resulting doped layers are characterized by exceedingly low carrier mobilities. The well‐known similar deficiency of pulse‐annealed implanted layers would thus appear to be caused by some artifact introduced by the pulse rather than by residual damage unannealed from the implantation. Pulse diffusion should provide an alternative means to implantation for forming n+ contacts in GaAs.