D.J. Fouts

A single-chip false target radar image generator for countering wideband imaging radars

This paper describes the theory, design, implementation, simulation, and testing of an ASIC capable of generating false target radar images for countering wideband synthetic aperture and inverse synthetic aperture imaging radars. The 5.5 /spl times/ 6.1 mm IC has 81632 transistors, 132 I/O pins, and consumes 0.132 W at 70 MHz from a 3.3-V supply. An introduction to the application and operation of the ASIC in an electronic attack system is also presented. The false target image is fully programmable and the chip is capable of generating images of both small and large targets, even up to the size of an aircraft carrier. This is the first reported use of all-digital technology to generate false target radar images of large targets.

Modeling single-event effects in a complex digital device

A methodology to quantify the impact of SEEs on complex digital devices has been developed. This methodology is based on the SEE State-Transition Model and was validated by radiation testing of a complex digital device.

Effects of low-temperature buffer-layer thickness and growth temperature on the SEE sensitivity of GaAs HIGFET circuits

Heavy-ion Single Event Effects (SEE) test results reveal the roles of growth temperature and buffer layer thickness in the use of a low-temperature grown GaAs (LT GaAs) buffer layer for suppressing SEE sensitivity in GaAs HIGFET circuits.

A picosecond-response photoconductive-sampling probe for digital circuit testing

Recent efforts in noninvasive high-frequency and high-resolution measurement techniques have led to the development of a number of photoconductive probes. In this paper the feasibility of using the fiber-coupled, micromachined probe for in-circuit testing and characterization is demonstrated by detecting waveforms at internal nodes of two different digital circuits. On the one hand, measurements have been carried out which reveal the performance of a circuit under standard operating conditions. In this case the measured electrical signals originate from an external source, i.e., an rf synthesizer. In a second application, femtosecond optical pulses have illuminated one of the transistors of a circuit to generate the signal that is measured. This second approach is used to emulate so-called single-event upsets (SEU), which are usually caused by cosmic particles in satellite-based electronic systems. These effects have a negative impact on the performance and reliability of these systems and therefore are a limiting factor for their commercial implementation. In the past, optical techniques to generate SEU effects have been successfully demonstrated for testing single devices. In contrast, the results presented here demonstrate the generation and detection of these effects inside a complex circuit environment. Thus, they may especially benefit the development of radiation-immune circuits.

SEU design considerations for MESFETs on LT GaAs

Computer simulation results are reported on transistor design and single-event charge collection modeling of metal-semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII(R) process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU) immunity and transistor design are discussed. Effects due to active loads and diffusion barriers are examined.

Single event upsets in gallium arsenide dynamic logic

The advantages and disadvantages of using gallium arsenide (GaAs) dynamic logic in computers and digital systems are briefly discussed, especially with respect to space applications. A short introduction to the topology and operation of GaAs Two-Phase Dynamic FET Logic (TDFL) circuits is presented. Experiments for testing the SEU sensitivity of GaAs TDFL, using a laser to create charge collection events, are described. Results are used to estimate the heavy-ion, soft error rate for TDFL in a spacecraft in geosynchronous orbit, and the dependence of the SEU sensitivity on clock frequency, clock voltage, and clock phase. Analysis of the data includes a comparison between the SEU sensitivities of TDFL and the more common static form of GaAs logic, Directly Coupled FET Logic (DCFL). This is the first reported SEU testing of GaAs dynamic logic. >

Efficient time-frequency and bi-frequency signal processing on a reconfigurable computer

Reconfigurable computers allow applications developers to tailor both the software and the hardware of the computer for efficient execution of computationally intensive algorithms. This increases the speed at which the algorithms are executed, making computationally intensive algorithms more useful for real-time and near real-time applications in electronic intelligence (ELINT) applications. This paper presents a study on the use, accuracy, and efficiency of the SRC-6 reconfigurable computer to perform both time-frequency and bi-frequency signal processing. To test the performance, continuous waveform (CW) radar signal modulations are examined using the Choi-Williams distribution (CWD) to calculate the time-frequency characteristics of a signal. Also, the FFT accumulation method (FAM) is used to calculate the cyclostationary bi-frequency characteristics of a signal.

A CMOS current-mode full-adder cell for multi-valued logic VLSI

This paper describes the design and implementation of a carry save adder cell for multi-valued logic (module 4) VLSI using the HAMLET CAD tool. A VLSI test and evaluation integrated circuit was implemented with MAGIC, simulated using SPICE, and fabricated through the MOSIS service. Engineering modifications to the original current-mode inverter cells used by HAMLET were made leading to significant power savings in a complete design. The fabricated device performed as predicted by SPICE simulation.

Memory latency reduction using an address prediction buffer

A novel approach to improving memory system performance is the use of a memory prediction buffer (MPB). The MPB is inserted between the cache and main memory. The MPB predicts the next cache-miss address and prefetches the data. The use of an MPB in a computer system is shown to decrease memory latency and increase system performance. The MPB outperforms prefetch always strategies by allowing addressing in the up and down direction. In addition, the MPB does not contribute to pollution of the cache. Only demand information is taken from the MPB to the cache. The implementation of a MPB is less expensive than a next-level cache and delivers a comparable performance enhancement.<<ETX>>

Soft error immune GaAs circuit technologies

Cosmic radiation induced soft errors present a major difficulty for space applications that utilize digital GaAs circuits and systems. Techniques to reduce soft error sensitivity by 5 orders of magnitude or more, to sufficient levels for safe implemention of GaAs ICs in space applications are presented. These results show that the need for redundancy and error correction is eliminated. Space systems will benefit by reduced power and area requirements, plus a substantial improvement in system performance over present radiation hardened silicon-based technologies.