Phillip E. Pace
Naval Postgraduate School
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Featured researches published by Phillip E. Pace.
asilomar conference on signals, systems and computers | 2008
Gerald L. Fudge; Ross E. Bland; Mark A. Chivers; Sujit Ravindran; Jarvis D. Haupt; Phillip E. Pace
Many radar and communications applications require detection and estimation of signal information across an extremely wide radio frequency (RF) bandwidth. In practice, however, direct digitization of this broadband RF environment is problematic. Physical limitations in analog-to-digital converter (ADC) technology restrict the total bandwidth that can be digitized, as well as the ability to digitize high RF signals directly. This paper describes a novel ldquoanalog-to-informationrdquo receiver, motivated by recent developments in compressed sensing (CS), which overcomes both of these challenges in certain settings. The proposed receiver performs frequency modulated pulsed sampling at sub-Nyquist/Shannon rates to compress a broadband RF environment into an analog interpolation filter. The RF sample clock modulation induces a Nyquist-zone dependent frequency modulation on the received signals, allowing separation and recovery of the signal information from a sparse broadband RF environment.
IEEE Transactions on Signal Processing | 1997
Phillip E. Pace; Richard E. Leino; David Styer
The relationship between the discrete Fourier transform (DFT) and the symmetrical number system (SNS) is examined as a means of resolving single-frequency undersampling aliases (f>f/sub s//2). It is shown that the DFT naturally encodes the frequency information of a signal in a format that is in the same form as the SNS. Consequently, aliases that result from undersampling a signal can be resolved exactly using r/spl ges/2 channels. To demonstrate the concept, two- and three-channel examples are presented. Using the SNS properties of the DFT, the undersampling aliases can be easily resolved to a much greater extent than previously possible.
Optical Engineering | 1994
Phillip E. Pace; David Styer
A technique is described for extending the resolution of an integrated optical multi-interferometer guided-wave analog-to-digital converter. The optical output waveform for each interferometer is symmetrically folded at twice a proper modulus. A small comparator ladder mid-level quantizes each interferometers detected output to encode the analog signal in a symmetrical number system (SNS) format. By incorporating the SNS encoding, resolution greater than 1 bit per interferometer can be provided. Analog signal levels that can cause possible encoding errors are examined and their impact on the overall amplitude analyzing function is discussed. The maximum laser pulse width and maximum fluctuation in the sampling interval that can be tolerated is also discussed. Results indicate that 11-bit resolution can be provided with three interferometers and 39 comparators.
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing | 2000
Phillip E. Pace; D. Styer; I.A. Akin
A folding analog-to-digital converter (ADC) preprocessing architecture based on a new robust symmetrical number system (RSNS) is presented. The RSNS preprocessing architecture is a modular scheme in which the integer values within each modulus (comparator states), when considered together, change one at a time at the next position (gray-code properties). Although the observed dynamic range of the RSNS ADC is less than the optimum symmetrical number system ADC, the RSNS gray-code properties make it particularly attractive for error control. With the RSNS preprocessing, the encoding errors due to comparator thresholds not being crossed simultaneously are eliminated. As a result, the interpolation circuits can be removed and only a small number of comparators are required. Computer generated data is used to help determine the properties of the RSNS. These properties include the dynamic range (largest number of distinct consecutive vectors) and the location of the dynamic range within the number system. Closed-form expressions for the dynamic range are also presented for channel moduli of the form m/sub 1/=2/sup k/-1, m/sub 2/=2/sup k/, m/sub 3/=2/sup k/+1. RSNS ADC circuit design principles are presented. To compare the advantages of the RSNS ADC with previously published results, the transfer function of a 3-channel architecture (k=2) is evaluated numerically using SPICE.
IEEE Transactions on Antennas and Propagation | 2001
Phillip E. Pace; David Wickersham; David C. Jenn; Nathan S. York
This paper identifies a new phase sampling interferometer approach that can he easily incorporated into the established techniques to provide a high resolution, small-baseline array with a fewer number of phase sampling comparators. The approach is based on preprocessing the received signal using symmetrical number systems (SNS). Antennas based on both an optimum symmetrical number system (OSNS) and a robust symmetrical number system (RSNS) are investigated. The SNS preprocessing is used to decompose the spatial filtering operation into a number of parallel suboperations (moduli) that are of smaller computational complexity. A much higher direction finding (DF) spatial resolution is achieved after the N different moduli are used and the results of these low precision suboperations are recombined. By incorporating the OSNS or RSNS preprocessing concept, the field of view of a specific configuration of interferometers and phase sampling comparator arrangements can be analyzed exactly. The OSNS gives the maximum dynamic range or number of spatial resolution bins while the RSNS reduces considerably the number of possible encoding errors. Experimental results for both a 5-bit OSNS and a 6-bit RSNS array are compared. The errors in the encoding of the direction of arrival are quantified for both architectures.
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing | 1994
Phillip E. Pace; P. A. Ramamoorthy; D. Styer
High performance analog-to-digital converters (ADCs) employ a parallel configuration of analog folding circuits to symmetrically fold the input signal prior to quantization by high speed comparators (analog preprocessing). This paper identifies a new preprocessing approach that can be easily incorporated into the established techniques to provide an enhanced resolution capability with fewer number of comparators loaded in parallel. The approach is based on preprocessing the analog signal with a symmetrical number system (SNS). The SNS preprocessing is used to decompose the analog amplitude analyzer operation into a number of sub-operations (moduli) which are of smaller computational complexity. Each sub-operation symmetrically folds the analog signal with folding period equal to the moduli. Thus, each sub-operation only requires a precision in accordance with that modulus. A much higher resolution is achieved after the N different SNS moduli are used and the results of these low precision sub-operations are recombined. By incorporating the SNS folding concept, the dynamic range of a specific configuration of folding periods and comparator arrangements can be analyzed exactly. >
IEEE Journal of Solid-state Circuits | 2002
D.J. Fouts; Phillip E. Pace; C. Karow; Stig R. T. Ekestorm
This paper describes the theory, design, implementation, simulation, and testing of an ASIC capable of generating false target radar images for countering wideband synthetic aperture and inverse synthetic aperture imaging radars. The 5.5 /spl times/ 6.1 mm IC has 81632 transistors, 132 I/O pins, and consumes 0.132 W at 70 MHz from a 3.3-V supply. An introduction to the application and operation of the ASIC in an electronic attack system is also presented. The false target image is fully programmable and the chip is capable of generating images of both small and large targets, even up to the size of an aircraft carrier. This is the first reported use of all-digital technology to generate false target radar images of large targets.
IEEE Transactions on Circuits and Systems I-regular Papers | 2002
D. Styer; Phillip E. Pace
Symmetrical number systems have been explored for many applications in both analog and digital signal processing due to the common availability of symmetrical folding waveforms (e.g., cos/sup 2/). The robust symmetrical number system (RSNS) is a modular scheme in which the integer values within each modulus, when considered together, change one at a time at the next code position (Gray code properties). Although the RSNS has a smaller dynamic range than the optimum symmetrical number system, the RSNS Gray code properties make it particularly attractive for error control. In the past, computer search algorithms have been used to determine the RSNS dynamic range (length of unambiguous vectors). In this brief, we define the two-channel RSKS and present a theorem that gives its dynamic range for relatively prime moduli m/sub 1/, m/sub 2/, 5 /spl les/ m/sub 1/ /spl les/ m/sub 2/.
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing | 1995
Phillip E. Pace; J.L. Schafer; D. Styer
Folding analog-to-digital converters (ADCs) that use symmetrical number system (SNS) preprocessing, require fewer comparators than those that use conventional binary encoding. This paper considers an alternate SWS definition that considerably extends the dynamic range of the SNS ADC. The efficiency of this definition is compared to previous definitions and is shown to be optimum. As an example, a unipolar 7-b SNS ADC using pairwise relatively prime moduli m/sub 1/=4, m/sub 2/=5 and m/sub 3/=7 is evaluated numerically. Transfer functions are shown which detail encoding errors that occur when the folded input samples lie at one of the code transition points. To discard the encoding errors that occur, a decimation band is constructed at each transition point. The effectiveness of the decimation band in eliminating the encoding errors is also quantified.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 2012
Ray Maleh; Gerald L. Fudge; Frank A. Boyle; Phillip E. Pace
Recovering even a small amount of information from a broadband radio frequency (RF) environment using conventional analog-to-digital converter (ADC) technology is computationally complex and presents significant challenges. For sparse or compressible RF environments, an alternate approach to conventional sampling is analog-to-information (A2I) to enable sub-Nyquist rate sampling based on compressive sensing (CS) principles. This paper presents the Nyquist Folding Receiver (NYFR), an efficient A2I architecture that folds the broadband RF input prior to digitization by a narrowband ADC. The folding is achieved by undersampling the RF spectrum with a stream of short pulses that have a phase modulated sampling period. The undersampled signals then fold down into a low pass interpolation filter. The pulse sample time modulation induces a corresponding phase modulation on the received signals that is scaled by an integer modulation index that varies with the Nyquist zone (i.e., fold number), allowing the signals to be separated based on the measured modulation index. Unlike many schemes motivated by CS that randomize the RF prior to digitization, the NYFR substantially preserves signal structure. This enables information recovery with very low computational complexity algorithms in addition to traditional CS reconstruction techniques. The paper includes a comparison of seven other A2I architectures with the NYFR.