D. M. H. Walker

Improved wafer-level spatial analysis for I/sub DDQ/ limit setting

This paper proposes a new methodology for estimating the upper bound on the I/sub DDQ/ of defect free chips by using wafer level spatial information. This can be used for I/sub DDQ/ pass/fail limit setting. This methodology is validated using SEMATECH data. Such a methodology accounts for the change in I/sub DDQ/ due to process variations across wafers and reduces false rejects resulting in yield loss. Typical scenarios in using this approach are discussed. The results are compared with traditional methods.

Dynamic Compaction for High Quality Delay Test

Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality.

A practical built-in current sensor for I/sub DDQ/ testing

This paper describes a new built-in current sensor (BICS) design, comprised of a MAGFET current sensor, stochastic sensor, self-calibration tool, counter, and scan chain. By indirectly measuring the current, the sensor avoids the unacceptable drawbacks of past BICS designs. Test chips fabricated in 180 nm and 250 nm technology demonstrate that the sensor can be used for IDDQ testing of large, high-performance, deep submicron circuits. This sensor should extend practical IDDQ testing to the 35 nm technology generation.

Modeling Power Supply Noise in Delay Testing

Excessive power supply noise during test can cause overkill. This article discusses two models for supply noise in delay testing and their application to test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing power noise analysis tools. can cause performance degradation and

Neighbor current ratio (NCR): a new metric for I/sub DDQ/ data analysis

I/sub DDQ/ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault free currents. The concept of current ratios, in which the ratio of maximum to minimum I/sub DDQ/ is used to screen faulty chips, has been previously proposed. The neighboring chips on a wafer have similar fault free properties and are correlated. In this paper, the use of spatial correlation in combination with current ratios is investigated. By differentiating chips based on their nonconformance to local I/sub DDQ/ variation, outliers are identified. The analysis of SEMATECH data is presented.

Yield learning via functional test data

This paper presents a methodology to estimate the defect Pareto in an IC process through the use of production functional test data. This Pareto can then be used for yield improvement activities. We demonstrate the concept on several benchmark circuits. We show how limited IDDQ current testing can significantly improve the Pareto accuracy.

A fast algorithm for critical path tracing in VLSI digital circuits

An exact, linear-time critical path tracing algorithm is presented. The performance of critical path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of nets.

Use of multiple I/sub DDQ/ test metrics for outlier identification

With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for I/sub DDQ/ test due to increased spread in the distribution. In this paper, the concept of current ratio is extended to exploit wafer-level spatial correlation. Two metrics - current ratio and neighbor current ratio - are combined to screen outliers at the wafer level. We demonstrate that a single metric alone cannot screen all outliers, however, their combination can be used for effectively screening outlier chips. Analyses based on industrial test data are presented.

I/sub DDQ/ test using built-in current sensing of supply line voltage drop

A practical built-in current sensor (BICS) is described that senses the voltage drop on supply lines caused by quiescent current leakage. This noninvasive procedure avoids any performance degradation. The sensor performs analog-to-digital conversion of the input signal using a stochastic process, with scan chain readout. Self-calibration and digital chopping are used to minimize offset and low frequency noise and drift. The measurement results of a 350 nm test chip are described. The sensor achieves a resolution of 182 muA, with the promise of much higher resolution

Comparison of Delay Tests on Silicon

Testing longer paths in an integrated circuit with a proper path selection strategy has the potential to increase the quality of a delay test. However, the benefit on silicon is not completely clear because a theoretical test quality increase is normally simulated using an assumed distribution of defect sizes. In this work, silicon data is collected and maximum operating frequency (Fmax) compared using test patterns generated by a variety of delay test methodologies. The silicon data is consistent with theoretical predictions and the benefits of testing delay faults through the longest path are quantified