Chadwin D. Young

The effect of interfacial layer properties on the performance of Hf-based gate stack devices

The influence of Hf-based dielectrics on the underlying SiO2 interfacial layer (IL) in high-k gate stacks is investigated. An increase in the IL dielectric constant, which correlates to an increase of the positive fixed charge density in the IL, is found to depend on the starting, pre-high-k deposition thickness of the IL. Electron energy-loss spectroscopy and electron spin resonance spectra exhibit signatures of the high-k-induced oxygen deficiency in the IL consistent with the electrical data. It is concluded that high temperature processing generates oxygen vacancies in the IL responsible for the observed trend in transistor performance.

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

Mechanism of Electron Trapping and Characteristics of Traps in

Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.

\hbox{HfO}_{2}

A methodology to analyze charge pumping (CP) data, which allows positions of probing traps in the dielectric to be identified, was applied to extract the spatial profile of traps in SiO2∕HfO2 gate stacks. The results suggest that traps accessible by CP measurements in a wide frequency range, down to few kilohertz, are located within or near the interfacial SiO2 layer rather than in the bulk of the high-k film.

Gate Stacks

We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO2 interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric

Response of the high-k gate dielectrics to low voltage stresses was studied by probing high-k transistors with various voltage/time measurements at different temperatures. The observed dependence of the transistor threshold voltage on stress time was attributed to electron trapping at pre-existing defects in the high-k dielectric rather than stress-induced trap generation. The dominance of the contribution from the reversible electron trapping on the pre-existing defects in the low voltage stress response raises the question on the applicability of the conventional reliability assessment methodology to the high-k dielectrics.

Interfacial Layer-Induced Mobility Degradation in High-

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moores Law towards the 10-nm physical gate length regime.

k

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO 2/HfO2 gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO2 layer and HfO2/SiO2 interface region. The trap density in the SiO2 layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO2 layer

Transistors

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.