D. Normanov

Development of the read-out ASIC for muon chambers of the CBM experiment

A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power comsumption of 10 mW per channel, 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consunption at 50 Msps. The chip also includes the threshold DAC and the digital part.

Development and experimental study of the readout ASIC for muon chambers of the CBM experiment

The measurement results of the front-end ASIC for the GEM detector read-out are presented. The MUCH ASIC v2 was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators, were measured. The channels provide a sufficient dynamic range of 100 fC, low power consumption of 10 mW per channel and ENC of 1550 el at a 50 pF detector capacitance.

Readout channel with majority logic timestamp and digital peak detector for Muon Chambers of the CBM experiment

A prototype readout channel was manufactured in UMC CMOS 180 nm for the purpose of the CBM experiment at the FAIR accelerator. The channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, a 6-bit SAR ADC (DNL = 0.70, INL = 0.45), digital peak detector and block of the time stamp registration. The control data, clock and output data are supplied through SLVS transmitter and receiver. The slow and fast channels have 1000 el and 1500 el ENC accordingly at a 50 pF detector capacitance. Power consumption is 10 mW/channel.

Area-efficient low-power 8-bit 20-MS/s SAR ADC in 0.18μm CMOS

This paper presents the design results of the prototype IP block of the successive approximation analog-to-digital converter (SAR ADC) for implementation by 0.18 um MMRF CMOS technology of UMC (Taiwan). Primarily the ADC unit was designed according to the technical requirements for the readout electronics of the silicon tracking system of the Compressed Baryonic Matter experiment at accelerator facility FAIR (www.gsi.de/en/research/fair.htm). However it can be used for a wider range of applications. To increase accuracy and ensure ADC resolution a rail-to-rail comparator was used. The SAR ADC occupies on chip area of 325μm × 325μm, ENOB is 6.88 bits, maximum DNL less than 0.8 LSB, an INL less than 0.6 LSB, sampling frequency - 20 MHz, clock frequency - 200 MHz, and SNDR is 43.2 dB. With these parameters the ADC consumes about 1.3 mA at a nominal supply voltage of 1.8V.

Development of the multichannel data processing ASIC design flow

In modern multichannel data processing digital systems the number of channels ranges from some hundred thousand to millions. The basis of the elemental base of these systems are ASICs. Their most important characteristics are performance, power consumption and occupied area. ASIC design is a time and labor consuming process. In order to improve performance and reduce the designing time it is proposed to supplement the standard design flow with an optimization stage of the channel parameters based on the most efficient use of chip area and power consumption.

Development of the asynchronous readout ASIC for GEM detectors

Currently the multichannel readout chip for GEM detectors with an asynchronous architecture is being developed. The readout channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, a 6 bit SAR ADC (40 Msps rate, 1.5 mW power consumption), digital peak detector and block of the time stamp registration. The digital peak detector has a feature, preventing the false peak detection. The final chip version is considered to be compatible with the GBTx data processing board. Thus, the control data, clock and output data are supplied through SLVS transmitter and receiver. The slow and fast channels have 1500 el and 2000 el ENC accordingly at a 50 pF detector capacitance. Power consumption is 10 mW/channel. The paper describes the last results in building blocks schematic and layout design, test benches and the results of the lab study.

The read-out ASIC for silicon drift detectors

The paper describes the read-out ASIC for silicon X-ray drift detectors. The ASIC has been designed in CMOS 0.35 μm technology and contains two read-out channels. Each channel includes a preamplifier and shaper. The preamplifier in the first channel has a built-in input transistor, the preamplifier in second channel works with an external JFET, which is built in the detector structure. Preamplifiers have been optimized for operation with detectors with capacitances of 100 fF. The 6-th order shaper has controllable time constants (0.5 - 8 μs).

Architecture of the multichannel data-driven ASIC

The development architecture of a multichannel data-driven ASIC is presented. It provides the selection of useful events at an early stage of reading out detector signals. The architecture is based on fast cross-point switches of analog signals, followed by their digitization by a limited set of ADCs and high-speed output data serialization. Such approach reduces the number of subsequent ADCs as well as digital processing channels. That leads to lower power consumption and chip area. The results of a prototype ASIC development, based on this architecture and intended for the CBM experiment at FAIR, are given.

Development of the read-out ASIC for muon chambers

A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.

Low-noise analog readout channel for SDD in X-ray spectrometry

A low-noise analog readout channel optimized for operation with the Silicon Drift Detectors (SDDs) with built-in JFET is presented. The Charge Sensitive Amplifier (CSA) operates in a pulse reset mode using the reset diode built-in the SDD detector. The shaper is a 6th order semi-Gaussian filter with switchable discrete shaping times. The readout channel provides the Equivalent Noise Charge (ENC) of 12e- (simulation) and input dynamic range of 30 keV . The measured energy resolution at the 5,89 keV line of a 55Fe X-ray source is 336 eV (FWHM). The channel was prototyped via Europractice in the AMS 350 nm process as miniASIC. The simulation and first measurement results are presented in the paper.