E. Atkin

Development of the read-out ASIC for muon chambers of the CBM experiment

A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power comsumption of 10 mW per channel, 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consunption at 50 Msps. The chip also includes the threshold DAC and the digital part.

A preamplifier for the muon system of the CBM experiment

The structure and results of the experimental study of the application specific integrated circuit, which contains two versions of a preamplifier for reading out and preprocessing signals of muon chambers, are presented. An integrated circuit was designed for operation in the muon system of the International Compressed Baryonic Matter (CBM) experiment at the FAIR accelerator facility (Darmstadt, Germany). It was manufactured by the CMOS technology with 0.18-μm design rules of the UMC company (Taiwan) via the Europractice European organization.

A study of the coordinate gas-filled detectors based on the GEM and TGEM technologies for the muon tracking system of the CBM experiment

Prototypes of the gas-filled detectors based on the GEM and TGEM technologies have been studied in the multistage gas amplification circuit with the aim of selecting variants for tracking detectors of the muon system capable of operating at high counting rates in the CBM experiment. Two- and three-component mixtures based on Ar and He are used as the working gas. Their key characteristics are presented. The gas amplification factors are measured for various high-voltage modes. The charge collection times determining the response speed of the tested detectors are estimated.

Testing a 32-channel integrated circuit for recording signals of silicon detectors

A 32-channel integrated microcircuit for microstrip silicon detectors of the “Nuklon” project for studying ionizing radiation in space conditions is tested. The microcircuit allows one to record signals of relativistic particles and nuclei with a charge from Z = 1 up to Z > 50 from silicon detectors. A structural diagram of the microcircuit and its main experimental characteristics are given. The power consumption does not exceed 1.5 mW/channel, and the dynamic range of recorded signals is not smaller than 100 pC.

Development and experimental study of the readout ASIC for muon chambers of the CBM experiment

The measurement results of the front-end ASIC for the GEM detector read-out are presented. The MUCH ASIC v2 was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators, were measured. The channels provide a sufficient dynamic range of 100 fC, low power consumption of 10 mW per channel and ENC of 1550 el at a 50 pF detector capacitance.

Read-out ASIC for microstrip detectors

The main results of designing a 32-channel integrated microcircuit for microstrip detectors of the Nuclon Project of Roskosmos are considered. The microcircuit is implemented by using 0.35 μm CMOS technology of AMIS (Belgium). The description of the integrated microcircuit and its main electrical parameters, features of the circuit technology, and crystal topology are presented. Record parameters of the dynamic range of readable signals (more than 100 pC) with a detector capacity of up to 100 pF exhibited by the microcircuit.

Readout channel with majority logic timestamp and digital peak detector for Muon Chambers of the CBM experiment

A prototype readout channel was manufactured in UMC CMOS 180 nm for the purpose of the CBM experiment at the FAIR accelerator. The channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, a 6-bit SAR ADC (DNL = 0.70, INL = 0.45), digital peak detector and block of the time stamp registration. The control data, clock and output data are supplied through SLVS transmitter and receiver. The slow and fast channels have 1000 el and 1500 el ENC accordingly at a 50 pF detector capacitance. Power consumption is 10 mW/channel.

A study of the coordinate gas-filled detectors based on the Micromegas and Micromegas + GEM/TGEM technologies for the muon tracking system of the CBM experiment

Prototypes of the gas-filled detectors produced on the basis of the Micromegas technology, as well as in combination with the Micromegas + GEM/TGEM structures in the multistage gas amplification circuit have been investigated with the aim of selecting variants for tracking detectors of the muon system designed for operating at high counting rates in the Compressed Baryonic Matter (CBM) experiment. Two- and three-component Ar- and He-based mixtures have been tested as the working gas. Their key characteristics are presented. The gas amplification factors are measured for various high-voltage modes, and the charge collection times determining the response speed of the tested detectors are estimated.

A procedure for optimizing the power consumption of a charge-sensitive amplifier

Problems of optimizing of the power consumption of a CMOS charge-sensitive amplifier for reading out the signals of multichannel silicon and gas detectors with capacitances up to 100 pF are discussed. In multichannel systems, the power consumption of electronics is limited. In this case it is required to achieve the optimal set of parameters of a charge-sensitive amplifier, and, in the first place, not to exceed the permissible noise and power consumption levels. The procedure for optimizing the parameters of the input transistor for reaching the minimal power consumption at the specified noise level of the charge-sensitive amplifier is described.

Area-efficient low-power 8-bit 20-MS/s SAR ADC in 0.18μm CMOS

This paper presents the design results of the prototype IP block of the successive approximation analog-to-digital converter (SAR ADC) for implementation by 0.18 um MMRF CMOS technology of UMC (Taiwan). Primarily the ADC unit was designed according to the technical requirements for the readout electronics of the silicon tracking system of the Compressed Baryonic Matter experiment at accelerator facility FAIR (www.gsi.de/en/research/fair.htm). However it can be used for a wider range of applications. To increase accuracy and ensure ADC resolution a rail-to-rail comparator was used. The SAR ADC occupies on chip area of 325μm × 325μm, ENOB is 6.88 bits, maximum DNL less than 0.8 LSB, an INL less than 0.6 LSB, sampling frequency - 20 MHz, clock frequency - 200 MHz, and SNDR is 43.2 dB. With these parameters the ADC consumes about 1.3 mA at a nominal supply voltage of 1.8V.