D. Passuello

The AMchip: a full-custom CMOS VLSI associative memory for pattern recognition

An associative memory full custom CMOS VLSI chip (AMchip), to be used in fast trigger systems for pattern recognition has been designed and is being successfully tested at INFN in Pisa. The AMchip is the first full-custom associative memory IC developed for high-energy physics. It contains about 140000 MOS transistors, has been realized in 1.5- mu m, double-metal, silicon gate CMOS technology, and is housed in a 120-pin package. The AMchip has been designed to be used with any kind of detector which provides output in hits coordinates, such as, for example, a silicon microstrip detector. The authors plan to realize a novel AMchip version using submicron technology and new circuit solutions, improving the pattern capacity by a factor 4, and significantly improving the speed. These versions will be developed to match new high-energy physics experiments specific requirements (for example, those of the Collision Detector Facility Silicon Vertex Tracker).<<ETX>>

The APE computer: An array processor optimized for lattice gauge theory simulations

Abstract The APE computer is a high performance processor designed to provide massive computational power for intrinsically parallel and homogeneous applications. APE is a linear array of processing elements and memory boards that execute in parallel in SIMD mode under the control of a CERN/SLAC 3081/E. Processing elements and memory boards are connected by a ‘circular’ switchnet. The hardware and software architecture of APE, as well as its implementation are discussed in this paper. Some physics results obtained in the simulation of lattice gauge theories are also presented.

The AMchip: a VLSI associative memory for track finding

Abstract An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1 × 1 cm 2 silicon chip.

The PeakSum Processing System for the NA48 experiment: a VLSI based processor

The PeakSum Processing System (PSS) is an element of the neutral trigger of the NA48 experiment at CERN. The PSS is a pipelined processor based on a VLSI semi-custom device, containing all the processing blocks needed in the system. The PSS provides information on the energy pattern released in the electromagnetic calorimeter of the NA48 experiment, used to identify K/sub 0//spl rArr//spl pi//sup 0//spl pi//sup 0//spl rArr/4/spl gamma/ decays.

The PeakSum system for the EPSI experiment

A system based on custom VLSI chips and working as peak counter, computing also the total energy, the barycenter and the second-order momentum functions, is being designed at INFN in Pisa. This system is intended to be used in the EPSI experiment trigger, but it can find more general applications. It is a pipelined circuit, designed to work with a pipeline clock period of 25 ns, but its components can be easily redesigned to have no internal pipeline stages.<<ETX>>

The PeakSum processing system for the NA48 experiment

The PeakSum Processing System (PSS) is an element of the neutral trigger of the NA48 experiment at CERN. The PSS is a pipelined processor based on a semi-custom device. It provides information on the energy pattern released. In the electromagnetic calorimeter of the experiment, used to discriminate K/sub S/ and K/sub L/ events.

The GLUEchip: a custom VLSI chip for detector readout and associative memories circuits

Summary form only. Designed to be used in associative memory circuits using the AMchip, the GLUEchip has found more general applications as a zero suppressor in wire-chambers and for calorimeter read-out for the EPSI (NA48) experiment at CERN. The GLUEchip is a custom VLSI CMOS chip realized in 1.5- mu m, silicon gate technology. It works as a pipelined priority encoder with special handshake circuitry. The prototypes run with a clock up to 30 MHz. Various versions, ranging from a 16-pin up to a 120-pin case, can be realized to optimize its use in specific applications. >

AMsystem: the associative memories readout system

The AMsystem has been designed having in mind mainly the track finding problem in the Collider Detector Facility (CDF) silicon vertex detector, and the trigger studies at fixed target and colliders (NAxx project at CERN). The AMsystem is conceived as a data driven device, where the input data are parallel streams of detector hit coordinates, and the output data are a list of recognized tracks. This allows the structure to be easily embedded in an existing trigger/data-acquisition system. The core of the system consists of a set of boards housing the AMchips and the GLUEchips (needed for tree-structuring the readout chain), and of a Sequencer board which controls the input/output (I/O) operations performed on each event. The I/O interfaces connect to the data acquisition system and to the experiment-specific data sources. All the boards are housed in a double Eurocard crate. VMEbus is used to control and download the AMsystem.<<ETX>>

The time history module: a FASTBUS-interfaced logical analyzer for detector monitoring and other applications

A first prototype of a FASTBUS-interfaced logical analyzer module usefully employable in detector and/or trigger system monitoring is described. Four of these time history modules (THMs) have been successfully utilized in the NA31 experiment at CERN from 1985 to 1989, principally to control the purity of the accepted events. These THMs have a built-in interface to the trigger system (based on finite state machine technique), a double input buffer and a 20-MHz sampling clock. The best features of the THM are the glitch capture, the fully programmable sampling time interval, the fast double-input buffer, the separate readout buffer, the data compression capability, the high time resolution, the FASTBUS block reading, and the easy and flexible triggering. Technological improvements are now possible in storage capacity, speed, programmability, and power dissipation. >

The Aleph trigger supervisor

The prototype of a FASTBUS master/slave, which in the Aleph experiment is the intelligent interface between the trigger system and the readout controllers, is described. It is based on two microprogrammable sequencers, one acting as a FASTBUS master and the other equipped with a 32-bit ALU (arithmetic logic unit); its internal registers/devices are time-shared by the two sequencers. The control part of the main protocol is implemented as two finite-state machines based on the PAL technique. >