F. Morsani

A time-over-threshold machine: the readout integrated circuit for the BABAR Silicon Vertex Tracker

A low-noise, mixed-signal, 128-channel CMOS integrated circuit containing the complete readout electronics for the BABAR Silicon Vertex Tracker has been developed. The outstanding feature of the present implementation is the ability to perform simultaneously low-level signal acquisition, derandomizing data storage, sparsification and data transmission on a single monolithic chip. The signals from the detector strips are amplified, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time of 100 ns, 200 ns, 300 ns, or 400 ns, and then presented to a time-over-threshold processor to implement a compression type analog-to-digital conversion. The digital information is stored, sparsified and read out through a serial link upon receipt of a command. The digital section operates from a 60 MHz incoming clock. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 k transistors. The first full-scale prototype was fabricated in a radiation soft 0.8 /spl mu/m, 3-metal CMOS process. The same circuit is now being fabricated in an analogous radiation hard technology.

Performance of the ALEPH Time Projection Chamber

Abstract The performance of the ALEPH Time Projection Chamber (TPC) has been studied using data taken during the LEP running periods in 1989 and 1990. After correction of residual distortions and optimisation of coordinate reconstruction algorithms, single coordinate resolutions of 173 μm in the azimuthal and 740 μm in the longitudinal direction are achieved. This results in a momentum resolution for the TPC of Δp / p 2 = 1.2 × 10 −3 (GeV/ c ) −1 . In combination with the ALEPH Inner Tracking Chamber (ITC), a total momentum resolution of Δp / p 2 = 0.8 × 10 −3 (GeV/ c ) −1 is obtained. With respect to particle identification, the detector achieves a resolution of 4.4% for the measurement of the ionisation energy loss.

SVT: an online silicon vertex tracker for the CDF upgrade

The SVT is an online tracker for the CDF upgrade which will reconstruct 2D tracks using information from the Silicon VerteX detector (SVXII) and Central Outer Tracker (COT). The precision measurement of the track impact parameter will then be used to select and record large samples of B hadrons. We discuss the overall architecture, algorithms, and hardware implementation of the system.

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Proposal of a data sparsification unit for a mixed-mode MAPS detector

The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.

An FPGA-based trigger system for the search of μ+→e++γ decay in the MEG experiment

The MEG experiment at PSI aims at investigating the μ+ → e+ + γ decay with improved sensitivity on the branching ratio (BR) by two orders of magnitude with respect to the previous experimental limit (BR(μ+ → e+ + γ) ≈ 10−13). The use of the most intense continuous muon beam world wide ( ≈ 108μ/s) to search for such a rare event must be accompanied by an efficient trigger system, able to suppress the huge beam-related background to sustainable rates while preserving the efficiency on signal close to unity. In order to accomplish both objectives, a digital approach was exploited by means of Field Programmable Gate Arrays (FPGA), working as a real-time processors of detector signals to perform an accurate event reconstruction within a 450 ns latency. This approach eventually turned out to be flexible enough to allow us to record calibration events in parallel with the main data acquisition and monitor the detector behavior throughout the data taking. We describe here the hardware implementation of the trigger and its main features as well: signal digitization, online waveform processing, reconstruction algorithms. A detailed description is given of the system architecture, the feature of the boards and their use. The trigger algorithms will be described in details in a dedicated article to be published afterwards.

The trigger for K0→π0π0 decays of the NA48 experiment at CERN

The trigger used for the collection of the samples of K0→π0π0 decays in the NA48 experiment at CERN uses a novel pipeline design in order to satisfy the demanding specifications of a high rate kaon beam. The trigger algorithms, architecture and performance are described.

Front-End Performance and Charge Collection Properties of Heavily Irradiated DNW MAPS

Deep N-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm technology have been exposed to γ-rays up to an integrated dose of about 10 Mrad and subjected to a 100 °C/168 h annealing cycle. Device tolerance to total ionizing dose has been evaluated by monitoring the change in charge sensitivity, noise and charge collection properties after each step of the irradiation and annealing campaign. Damage mechanisms and their relation to front-end architecture and sensor features are thoroughly discussed by comparing the response to ionizing radiation of different test structures and based on radiation induced degradation models in single MOS transistors.

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

A different approach to the design of CMOS MAPS has recently been proposed. By exploiting the triple well option of a CMOS commercial process, a deep n-well (DNW) MAPS sensor has been realized with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and a latch. This readout approach beeing compatible with data sparsification will improve the readout speed potential of MAPS sensors. The first protoype chips, realized with STMicroelectronics 130 nm triple well process, proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from 55Fe and electrons from 90Sr. Extensive tests performed to characterize the second generation of the APSEL chips based on the DNW MAPS design are reported. Small 3times3 pixel matrices with full analog output have been tested with radioactive sources to characterize charge collection. Pixel noise equivalent charge (ENC) of 50 e- and signal-to-noise ratio for MIPs of about 14 have been measured. Improved pixel noise and reduced threshold dispersion (about 100 e-) have been measured in the 8times8 matrix with a sequential readout. Based on the new DNW MAPS design a dedicated fast readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels.

Development of the YAP-PEM scanner for breast cancer imaging.

A prototype for positron emission mammography is under development at the Department of Physics of Pisa University. The device will be composed of two opposing detectors (parallel plane geometry). The active part of each detector head consists of a matrix of 900 YAP: Ce pixel scintillators, with a 2x2 mm(2) pitch and a 30 mm thickness. The read out is performed by an array of nine metal channel dynode PSPMTS (mod. R8520-00-C12) from Hamamatsu. In the previous version of the head, the PSPMTS were independently read out. For the clinical implementation of the prototype we have designed a simplified circuitry for the readout of the nine tubes based on a multiplexed resistive divider, reducing the number of channels from 36 to 4. A simulation study for an optimised amplifier has been carried out. The housing for each of the two yap-pem detectors has been fully engineered and is in the assembly stage.