D. Pogany

InAlN/GaN HEMTs: a first insight into technological optimization

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

We address degradation aspects of lattice-matched unpassivated InAlN/GaN high-electron-mobility transistors (HEMTs). Stress conditions include an off-state stress, a semi-on stress (with a partially opened channel), and a negative gate bias stress (with source and drain contacts grounded). Degradation is analyzed by measuring the drain current, a threshold voltage, a Schottky contact barrier height, a gate leakage and an ideality factor, an access, and an intrinsic channel resistance, respectively. For the drain-gate bias < 38 V parameters are only reversibly degraded due to charging of the pre-existing surface states. This is in a clear contrast to reported AlGaN/GaN HEMTs where an irreversible damage and a lattice relaxation have been found for similar conditions. For drain-gate biases over 38 V InAlN/GaN HEMTs show again only temporal changes for the negative gate bias stresses; however, irreversible damage was found for the off-state and for the semi-on stresses. Most severe changes, an increase in the intrinsic channel resistance by one order of magnitude and a decrease in the drain current by similar to 70%, are found after the off-state similar to 50 V drain-gate bias stresses. We conclude that in the off-state condition hot electrons may create defects or ionize deep states in the GaN buffer or at the InAlN/GaN interface. If an InAlN/GaN HEMT channel is opened during the stress, lack of the strain in the barrier layer is beneficial for enhancing the device stability.

Comprehensive Study of the Complex Dynamics of Forward Bias-Induced Threshold Voltage Drifts in GaN Based MIS-HEMTs by Stress/Recovery Experiments

The transient recovery characteristics of the threshold voltage drift (ΔVth) of GaN-based HEMTs with a SiO2 gate dielectric induced by forward gate bias stress are systematically and comprehensively investigated for stress times from 100 ns to 10 ks, recovery times from 4 μs to 10 ks, and stress biases from 1 to 7 V. The measured recovery data are analyzed using the concept of capture emission time maps. It is shown that the observed data cannot be explained by simple first-order defect kinetics. It is revealed that the recovery curves for constant stress times scale with the stress bias. Furthermore, the shape of the recovery curves changes from concave to convex with increasing stress time, independent of the stress bias. For short stress times and low stress bias, a dominant rate limiting effect of the III/N barrier layer is proposed. Defect-related physical processes with a broad distribution of characteristic time constants are discussed to explain the logarithmic time dependency of ΔVth stress and recovery, at which the role of the Coulomb feedback effect, complex defects, and spatially distributed defects are considered.

Towards understanding the origin of threshold voltage instability of AlGaN/GaN MIS-HEMTs

GaN-power HEMTs with insulated gate structure suffer from threshold voltage drifts (ΔVth) under forward gate bias stress. We present a systematical approach to characterize the phenomenon and understand the dominant physical mechanisms causing this effect. We found out that ΔVth is caused by traps with a broad distribution of trapping and emission time constants. This distribution is analyzed using so called Capture Emission Time (CET) maps known from the study of bias temperature instability (BTI) in CMOS devices. Physical models, which could explain the broad distribution of time constants, are discussed.

Transient thermal characterization of AlGaN/GaN HEMTs grown on silicon

We studied a temperature increase and a heat transfer into a substrate in a pulsed operation of 0.5 length and 150 /spl mu/m gate width AlGaN/GaN HEMTs grown on silicon. A new transient electrical characterization method is described. In combination with an optical transient interferometric mapping technique and two-dimensional thermal modeling, these methods determine the device thermal resistance to be /spl sim/70 K/W after 400 ns from the start of a pulse. We also localized the high-electron mobility transistor heat source experimentally and we extracted a thermal boundary resistance at the silicon-nitride interface of about /spl sim/7/spl times/10/sup -8/ m/sup 2/K/W. Thermal coupling at this interface may substantially influence the device thermal resistance.

Gate insulation and drain current saturation mechanism in InAlN/GaN metal-oxide-semiconductor high-electron-mobility transistors

The authors investigate 2μm gate-length InAlN∕GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS HEMTs) with 12nm thick Al2O3 gate insulation. Compared to the Schottky barrier (SB) HEMT with similar design, the MOS HEMT exhibits a gate leakage reduction by six to ten orders of magnitude. A maximal drain current density (IDS=0.9A∕mm) and an extrinsic transconductance (gme=115mS∕mm) of the MOS HEMT also show improvements despite the threshold voltage shift. An analytical modeling shows that a higher mobility of electrons in the channel of the MOS HEMT and consequently a higher number of electrons attaining the velocity saturation may explain the observed increase in gme after the gate insulation.

Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry

In the backside interferometric thermal mapping technique, an infrared (IR) laser beam probes the temperature-induced changes in the semiconductor refractive index inside a semiconductor device, which results in a change in the measured optical phase shift. In this paper, a theoretical analysis of the phase shift is reported. The focus is on nanosecond-to-microsecond time-scale thermal mapping during high current stress, as occurring e.g., during an electrostatic discharge (ESD) event or in some power applications. An analytical expression for phase shift is obtained from the analysis of the thermal diffusion equation. The phase shift is directly proportional to the two-dimensional (2-D) heat energy density in the semiconductor active region of the device. The phase shift is also expressed in terms of the local dissipated heat energy and the heat transferred to the device top and lateral sides. In addition, the space integral of the phase shift is expressed in terms of a total energy dissipated in the device and the total heat transferred from the semiconductor to the top device layers. The theory shows an excellent agreement with experimental data obtained for a p-n diode ESD protection structure working in the avalanche regime.

Low-frequency noise sources in as-prepared and aged GaN-based light-emitting diodes

The low-frequency noise sources are investigated in as-prepared and aged GaN light-emitting diodes (LEDs). Accelerated aging is performed by thermal (300h at 240°C) and electrical forward-bias stressing (20 and 50mA for 2500h). At low currents I<IRTS, where IRTS is a critical current, the low-frequency noise is dominated by random telegraph signal (RTS) noise on top of the 1∕f noise. An explanation is given for the giant relative current jumps ΔI∕I≈50% and an expression for IRTS is derived. The RTS noise in our devices is a less-sensitive diagnostic tool for studying the results of accelerated aging. Two components of the 1∕f noise were observed: one is related to the quantum-well junction and the other is due to series resistance noise. The two 1∕f spectra have different current dependences. It was found that the junction 1∕f noise is not significantly affected by aging. However, a strong increase in series resistance noise, by a factor of 60–800 compared to unstressed devices, is observed after strong e...

Ultrathin InAlN/AlN Barrier HEMT With High Performance in Normally Off Operation

We present GaN-based high electron mobility transistors (HEMTs) with a 2-nm-thin InAlN/AlN barrier capped with highly doped n++ GaN. Selective etching of the cap layer results in a well-controllable ultrathin barrier enhancement-mode device with a threshold voltage of +0.7 V. The n++ GaN layer provides a 290-Omega/\square sheet resistance in the HEMT access region and eliminates current dispersion measured by pulsed IV without requiring additional surface passivation. Devices with a gate length of 0.5-mum exhibit maximum drain current of 800 mA/mm, maximum transconductance of 400 mS/mm, and current cutoff frequency fT of 33.7 GHz. In addition, we demonstrate depletion-mode devices on the same wafer, opening up perspectives for reproducible high-performance InAlN-based digital integrated circuits.

Investigation of the thermal boundary resistance at the III-Nitride/substrate interface using optical methods

Heat removal from III-Nitride-based devices into a substrate depends also on an acoustic coupling at III-Nitride/substrate interface. We investigate thermal boundary resistance (TBR) and its effects on temperature distribution for GaN layers on Si, SiC, or sapphire substrates. Micro-Raman method is used for the investigation of TBR at the GaN/Si interface while the transient interferometric mapping (TIM) method is used for investigation of GaN/SiC and GaN/sapphire systems. Thermal modeling is used to analyze the experimental data. We found TBR to be ∼7×10−8 m2 K/W for GaN/Si and ∼1.2×10−7 m2 K/W for GaN/SiC interfaces. The role of TBR at the GaN/sapphire interface in the poor heat transfer from GaN to substrate is found to be less important. It is suggested that the substrate cooling efficiency may be improved if fewer defects are present at the interface to the GaN epistructure.