Gerhard Groos

Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry

In the backside interferometric thermal mapping technique, an infrared (IR) laser beam probes the temperature-induced changes in the semiconductor refractive index inside a semiconductor device, which results in a change in the measured optical phase shift. In this paper, a theoretical analysis of the phase shift is reported. The focus is on nanosecond-to-microsecond time-scale thermal mapping during high current stress, as occurring e.g., during an electrostatic discharge (ESD) event or in some power applications. An analytical expression for phase shift is obtained from the analysis of the thermal diffusion equation. The phase shift is directly proportional to the two-dimensional (2-D) heat energy density in the semiconductor active region of the device. The phase shift is also expressed in terms of the local dissipated heat energy and the heat transferred to the device top and lateral sides. In addition, the space integral of the phase shift is expressed in terms of a total energy dissipated in the device and the total heat transferred from the semiconductor to the top device layers. The theory shows an excellent agreement with experimental data obtained for a p-n diode ESD protection structure working in the avalanche regime.

Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry

A novel two-dimensional backside optical imaging method for thermal energy mapping inside semiconductor devices is presented. The method is based on holographic interferometry from the device backside and uses the thermo-optical effect. An image of the local thermal energy is obtained with 5-ns time resolution using a single stress pulse. The technique allows a unique recording of the internal device behavior. The method is demonstrated analyzing the nonrepetitive thermal and current flow dynamics in smart power electrostatic discharge (ESD) protection devices. A spreading of the current during the stress pulse is observed and explained by the effect of the negative temperature dependence of the impact ionization coefficient.

Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique

Abstract Spatial distribution of temperature and free-carrier concentration during high-current stress is studied in smart power electrostatic discharge (ESD) protection devices using a backside laser interferometric technique. The method is based on detecting changes in the refractive index of silicon due to thermo-optical and plasma-optical effects. We use a modified version of a heterodyne interferometer, where the reference beam is reflected from an external mirror outside the sample chip, which allows one to perform measurements without any restriction to the size of the scanning area. We have found two pronounced heat dissipating regions due to a vertical and a lateral current flow path in the device. In addition, two regions with increased current density due to carrier injection related to the two current paths have been found. These temperature and carrier concentration distributions found by the experiment agree very well with the results of 2D device simulation.

Measurement and modeling of the electron impact-ionization coefficient in silicon up to very high temperatures

In this paper, an experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge (ESD) conditions. Special test devices were designed and manufactured using Infineons SPT5 technology, namely: a bipolar junction transistor (BJT), a static-induction transistor (SIT) and a vertical DMOS transistor (VDMOS), all of them with a cylindrical geometry. The measurements were carried out using a customized measurement setup that allows very high operating temperatures to be reached. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature has been used. The experiments, carried out up to 773 K, confirm a previous theoretical investigation on impact-ionization, and widely extend the validity range of the compact model here proposed for implementation in device simulation tools. This is especially useful to predict the failure threshold of ESD-protection and power devices.

Extraction of spatio-temporal distribution of power dissipation in semiconductor devices using nanosecond interferometric mapping technique

A method for the extraction of power dissipation sources inside semiconductor devices on a nanosecond-time scale is proposed using a backside transient interferometric mapping technique. The two-dimensional power dissipation density is extracted from the time and space derivative of the measured optical phase shift. The method is applied to the analysis of moving current filaments in an electrostatic discharge protection device operating in the avalanche regime. It is found that the filament dynamics is governed by the negative temperature dependence of the impact ionization coefficient. The total power calculated from the optical measurements is in excellent agreement with the electrical input power.

Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection structures

Electro-thermal simulation and a laser-interferometric thermal mapping technique are employed to study temperature distribution and dynamics in smart power technology electrostatic discharge (ESD) protection npn transistor devices during a high current stress. The simulation predicts two temperature peaks along the device length which are due to a vertical and lateral current pathway in the studied devices. The temperature distribution in the device is studied via the measurements of the temperature-induced optical phase shift from the device backside. The position of the temperature peaks, their temporal evolution and stress level dependence obtained by experiment and simulation are in good agreement.

Experimental extraction of the electron impact-ionization coefficient at large operating temperatures

A theoretical and experimental investigation on the electron impact ionization in silicon has been carried out in the temperature range between 300 and 773 K. The impact-ionization model proposed here amply extends the range of simulation tools up to nearly 800 K, which is especially important in order to predict the failure threshold of ESD-protection and power devices.

Thermal distribution during destructive pulses in ESD protection devices using a single-shot two-dimensional interferometric method

Thermal distribution during single destructive electrostatic discharge (ESD) events is investigated in smart power ESD protection devices using a two-dimensional holographic interferometry technique. The hot spot dynamics and the position of destructive current filaments is correlated with the thermal distribution under the nondestructive conditions and with the failure analysis results.

A new numerical and experimental analysis tool for ESD devices by means of the transient interferometric technique

Two different protection diodes are investigated with electrothermal simulation and transient interferometric thermal-mapping experiments in a new complementary approach. The prediction capability of the simulation tool is validated up to the thermal failure of the p-n junction. The temperature distribution and its dynamics during the application of high-current pulses are studied by comparing the calculated and experimental optical phase shifts: a quantitative agreement both in temporal evolution and space distribution of temperature is obtained up to 1100 K.

Theory and experimental validation of a new analytical model for the position-dependent Hall Voltage in devices with arbitrary aspect ratio

A number of devices, that are under investigation for implementing and calibrating physical models at high operating temperatures and transient high current stress, exhibit geometrical features that do not allow for the application of the standard Hall theory. This makes the outcome of measurements based on the Hall effect unreliable. A more general theory has been developed, that leads to the determination of the Hall voltage as a function of the position along the longitudinal direction of the device channel. Devices with several pairs of Hall probes have been designed and manufactured, and the Hall voltage along their sides has carefully been measured. The experimental results led to a thorough validation of the theory.