D. R. Rolston

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Analysis of a Microchannel Interconnect Based on the Clustering of Smart-Pixel-Device Windows

A design analysis of a telecentric microchannel relay system developed for use with a smart-pixel-based photonic backplane is presented. The interconnect uses a clustered-window geometry in which optoelectronic device windows are grouped together about the axis of each microchannel. A Gaussian-beam propagation model is used to analyze the trade-off between window size, window density, transistor count per smart pixel, and lenslet ƒ-number for three cases of window clustering. The results of this analysis show that, with this approach, a window density of 4000 windows/cm(2) is obtained for a window size of 30 µm and a device plane separation of 25 mm. In addition, an optical power model is developed to determine the nominal power requirements of a 32 × 32 smart-pixel array as a function of window size. The power requirements are obtained assuming a complementary metal-oxide semiconductor inverter-amplifier and dual-rail multiple-quantum-well self-electro-optic-effect devices as the receiver stage of the smart pixel.

An optical backplane demonstrator system based on FET-SEED smart pixel arrays and diffractive lenslet arrays

We have demonstrated a representative portion of an optical backplane using FET-SEED smart pixels and free-space optics to interconnect printed circuit boards (PCBs) in a two board, unidirectional link configuration. 4/spl times/4 arrays of FET-SEED transceivers were designed, fabricated, and packaged all the PCB level, The optical interconnection was constructed using diffractive microoptics, and custom optomechanics. The system was operated in two modes, one showing high data throughput, 100 MBit/sec, and the other demonstrating large connection densities, 2222 channel/cm/sup 2/.<<ETX>>

A hybrid-SEED smart pixel array for a four-stage intelligent optical backplane demonstrator

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.

Design, modeling, and characterization of FET-SEED smart pixel transceiver arrays for optical backplanes

The design, modeling, and characterization of FET-SEED smart pixel transceiver arrays fabricated for application in optical backplanes are presented. Results of digital and analog measurements on 4/spl times/4 transmitter arrays and 4/spl times/4 receiver arrays, packaged at the printed circuit-board level, will be presented. In addition, these results will be compared to device and circuit models developed for these optoelectronics. Finally, the description of the successful application of these optoelectronics to interconnect two printed circuit boards will be described.

Six-degrees-of-freedom alignment of two-dimensional array components by use of off-axis linear Fresnel zone plates

A novel six-degrees-of-freedom (six-DOFs) alignment technique for assembling two-dimensional array components is presented. The technique uses off-axis linear Fresnel zone plates on one component that are combined with alignment targets on the other. The technique is compact and sensitive to all six DOFs; it was used to package an array of microlenses with a 32 x 32 array of GaAs multiple-quantum-well modulators flip-chip bonded to a 9 mm x 9 mm complementary-metal-oxide-semiconductor chip. By use of interference fringes to control the tilt misalignment, the worst-case misalignment of the microlenses relative to the chip is calculated to be as follows: lateral = 3.0 mum, rotational = 0.023 degrees , longitudinal = 13 mum, and tilt = 0.022 degrees . We also propose alternative implementations of the technique, including one that uses on-chip photodetectors to automate this six-DOF alignment technique.

Optical, optomechanical, and optoelectronic design and operational testing of a multi-stage optical backplane demonstration system

In this paper, we describe the optical, optomechanical, and optoelectronic design of a multistage optical backplane demonstration system. In addition, operational testing and performance is discussed.

BGA package integration of electrical, optical, and capacitive interconnects

We present a novel optically-enabled ball grid array (OBGA) package that integrates conventional electrical I/O, proximity communication (PxC), and optical communication in one industry-compatible BGA package for the first time. The key enabling technologies for such a packaging solution, including the precision alignment needed to combine multiple CMOS chips and compact opto-electronic (OE) subassemblies, are detailed here. We designed and fabricated a 45 mm × 45 mm × 5.2 mm organic cavity-down BGA package with up to 600 solder balls for electrical I/O. Its cavity holds three CMOS chips, with PxC interfaces and optical driver/receiver circuits, as well as two multi-channel optical subassemblies with standard optical fiber connections. We report preliminary testing results.

Design and testing of a kinematic package supporting a 32/spl times/32 array of GaAs MQW modulators flip-chip bonded to a CMOS chip

Innovative approaches to the design and packaging of a high-performance module supporting a 32/spl times/32 array of GaAs multiple quantum-well (MQW) modulators flip-chip bonded to a 9/spl times/9 mm/sup 2/ complementary metal-oxide-semiconductor (CMOS) chip are described. The module integrates a minilens array, a copper heat spreader, a thermoelectric cooler (TEC) and an aluminum heatsink. The minilens array is aligned and packaged with the chip using a novel six degrees of freedom (DOFs) alignment technique. The kinematic design allows for the manual insertion of the module into a free-space optical system with no need for further adjustments. The chip is mounted directly on a flexible printed circuit board (PCB) using a chip-on-board approach, providing over 200 bond pad connections to the chip. Impedance-controlled lines were operated at 1.0 Gb/s with a crosstalk of 4.0% between nearest neighbor lines. The junction-to-TEC thermal resistance is 0.4/spl deg/C/W, allowing for the use of a single-stage TEC to regulate the chip at an operating temperature of 40/spl deg/C under a maximum thermal load of 13.1 W.

A distributed synchronized clocking method

This paper will present a novel method to generate and distribute a synchronous clock to multiple nodes in a distributed system. Total system synchronization is established by adjusting the internal delays of each node so that the delay between all adjacent pairs of nodes becomes identical. The system is based on the principles of phase-locked and delay-locked loops but does not discuss the methods and details of phase acquisition, jitter or lock-in time. The system is composed of a master node used to generate clock pulses and multiple slave nodes used to align the pulses. A Matlab Monte Carlo simulation of the linear behavior of the system is presented which not only validates the theoretical description, but also can be used as a good tool to gauge the performance of any particular system scenario. Selected HSpice simulations are then presented which show the operating characteristics of certain scenarios involving differing interconnect lengths between nodes that correspond to specific Matlab simulations.